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I am new to this forum. I read a post where he Addis he was retrofitting a Kuhlmann machine with new electronics. I am in United States and have a Kuhlmann with a burnt board and need to get it running again. I think he might can give me some direction.

Upload some pictures of it here, also the electronics box and wiring pictures/PDF anything...

No spindle there, attach the hal and ini files here so we can have a look.

@meister, thanks.
I can only get linuxcnc top load if I revert to my original HAL, and with your suggestion the results of the grep spindle command are as in the screenshot 

From LinuxCNC documentation:

Still does not explain setting deadband causing a joint error.

I do not think so, and i never tried.
I use strictly Inkscape for plasma machines, it is easy to use and works perfectly fine, except for nesting that requires dividing cuts into layers and groups, so a bit more fiddly and i do not bother with it, it is easier for me to just edit the resulting gcode and move stuff around.

Hello I am new to this forum, but I have a Kuhlmann Engraver and a board died. I am looking for anyone who has information about converting it with new software and controllers.

 

Sounds all sensible to me but I really don't feel competent to comment on the proposed path.
I certainly like the structured approach of your initiative, that is something that has been sorely lacking in other attempts.
I think/hope that Rob will be able to give an educated opinion on it and shape it into a concrete roadmap.

Note that Mitsubishi SSCNET requires a servo cycle <= 222us
forum.linuxcnc.org/9-installing-linuxcnc...cnet?start=70#256576

Ruckig, I think we just need the math based on the math paper I think. Don't actually need to build the thing inside linuxcnc.
I proposed a minimum of 250us because that's what other users here expressed, otherwise you could run ruckig in the servo, but I thought better keep it out, even if advertised as 50us, some calculations seems known to exceed this advertisement. The handoff was my concept idea. Inspired by how CPU have predictive branching

my calculation of the DEADBAND value:

pid_setup["DEADBAND"] = round(1 / abs(joint_config["SCALE_OUT"]) * 2, 4)

works for me

Ok so before i am breaking everything do i need something else apart for the hostmot2-firmware/tree/master from the git in order to compile a framework?

In the first file that you send to me PCW you added 4biss chanel insted of 3 and "IOPortTag & x"03" & BISSTag & BISSClkEnPin, -- I/O 16 PIN 13"
i was curious about this line?

I was going for a conf like that for 7i76_7i74biss3d depending on that this line does.

use work.IDROMConst.all;

package PIN_7I76_7I74BISS3D_34 is
constant ModuleID : ModuleIDType :=(
(HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(BISSTag, x"00", ClockHighTag, x"03", BISSDataAddr&PadT, BISSNumRegs, x"00", BISSMPBitMask),
(QcountTag, x"02", ClockLowTag, x"01", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
(StepGenTag, x"02", ClockLowTag, x"05", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);


constant PinDesc : PinDescType :=(
-- Base func sec unit sec func sec pin -- external DB25
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 00 PIN 1
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 01 PIN 14
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 02 PIN 2
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 03 PIN 15
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 04 PIN 3
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 05 PIN 16
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 06 PIN 4
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 07 PIN 17
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 08 PIN 5
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 09 PIN 6
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 10 PIN 7
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 11 PIN 8
IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 12 PIN 9
IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 13 PIN 10
IOPortTag & x"00" & QCountTag & x"03", -- I/O 14 PIN 11
IOPortTag & x"00" & QCountTag & x"02", -- I/O 15 PIN 12
IOPortTag & x"00" & QCountTag & x"01", -- I/O 16 PIN 13

-- 26 HDR -- IDC DB25
IOPortTag & x"00" & BISSTag & BISSDataPin, -- I/O 17 PIN 1
IOPortTag & x"01" & BISSTag & BISSDataPin, -- I/O 18 PIN 14
IOPortTag & x"02" & BISSTag & BISSDataPin, -- I/O 19 PIN 2
IOPortTag & x"01" & SSerialTag & SSerialRX3Pin, -- I/O 03 PIN 15
IOPortTag & x"00" & BISSTag & BISSClkPin, -- I/O 21 PIN 3
IOPortTag & x"01" & BISSTag & BISSClkPin, -- I/O 22 PIN 16
IOPortTag & x"02" & BISSTag & BISSClkPin, -- I/O 23 PIN 4
IOPortTag & x"01" & SSerialTag & SSerialTX3Pin, -- I/O 07 PIN 17
IOPortTag & x"01" & SSerialTag & SSerialRX4Pin, -- I/O 08 PIN 5
IOPortTag & x"01" & SSerialTag & SSerialRX5Pin, -- I/O 09 PIN 6
IOPortTag & x"01" & SSerialTag & SSerialRX6Pin, -- I/O 10 PIN 7
IOPortTag & x"01" & SSerialTag & SSerialRX7Pin, -- I/O 11 PIN 8
IOPortTag & x"01" & SSerialTag & SSerialTX4Pin, -- I/O 12 PIN 9
IOPortTag & x"01" & SSerialTag & SSerialTX5Pin, -- I/O 13 PIN 10
IOPortTag & x"01" & SSerialTag & SSerialTX6Pin, -- I/O 14 PIN 11
IOPortTag & x"01" & SSerialTag & SSerialTX7Pin, -- I/O 15 PIN 12
IOPortTag & x"01" & SSerialTag & SSerialTXEn7Pin, -- I/O 16 PIN 13

Do you know of Freecad works for plasma cutting with freecad and linuxcnc?

I'm a bit weary of anything that comes out of AI.
Could you give a bit more background information as to how you came up with these outlines? In other words: Are these the result of conscious deliberation or is that a product of AI?

### Architecture Principles

**RT thread (250µs capable):** Only evaluates pre-computed polynomials. No planning, no Ruckig, no kinematics. Just `position = evaluate_polynomial(t)` and send to drives.

**Userspace:** All heavy computation. Ruckig, backward velocity pass, kinematics, blending. Not tied to servo cycle.

**Predictive Handoff:** When replanning is needed (feed override, etc), userspace plans from a predicted future state, not current state. RT continues executing until the handoff time, then seamlessly transitions. This decouples userspace latency from RT determinism.

**Buffer Management:** Track buffer in TIME, not segment count. Short segments and long segments treated appropriately.

I notice that you mention the use of 'ruckig', is this a decision you made or is that something AI suggested?
According to this statement (which I have not verified )the 'ruckig' library is not free for more advanced uses. (Not that this must necessarily be a deal breaker):
forum.linuxcnc.org/38-general-linuxcnc-q...nner?start=70#320906

[edit]
there seems to be a ''community" and a "pro" version of ruckig:
docs.ruckig.com/md_pages_2__intermediate__waypoints.html

There seems to be little information about the 'pro' version:
github.com/pantor/ruckig/issues/78

Again, something is not OK if you can change values of FFx and get no change in response, so are the drives set in "velocity" or "torque" mode?