my knowledge of verilog is extremely limited and i would be happy to have someone with me who is more familiar with it.
I'm the last person who would complain about someone getting things to work in RIO that I'm too stupid for
i will test the new driver later at home, the integration into RIO is not so hard.
all what rio 'know' about the w5500 plugin is here:
riocore/plugins/w5500/
so, more or less, copy the new files into this folder and editing plugin.py:
changing list of verilog files:
Code:
self.VERILOGS = ["w5500.v", "SPI.v"]
and add the new pin:
Code:
self.PINDEFAULTS = {
....
"w5500_rst": {
"direction": "output",
"invert": False,
"pull": None,
},
}
The only thing missing is this in the w5500.v:
Code:
input [BUFFER_SIZE-1:0] tx_data,
output [BUFFER_SIZE-1:0] rx_data,
output reg sync = 0,
output reg pkg_timeout = 0
sync: goes to 1 if a new package is received
pkg_timeout: goes to 1 if no package received for a while (parameter TIMEOUT)
tx_data: the data to send
rx_data: the received package
pkg_timeout is needed to trigger the error state of the CNC
sync is needed for multiplexed data
BUFFER_SIZE depends on the configuration and will be set while generating the rio.v
