LinuxCNC-RIO - RealtimeIO for LinuxCNC based on FPGA (ICE40 / ECP5)

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31 Jul 2024 18:47 #306556 by meister
now for you (MecanixDev board is addet to the dev branch):

generating from terminal:
PYTHONPATH=. bin/rio-generator riocore/configs/MecanixDev/config-test.json

gui-setup:
PYTHONPATH=. bin/rio-setup riocore/configs/MecanixDev/config-test.json
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31 Jul 2024 18:58 - 31 Jul 2024 19:01 #306557 by meister
I'm not quite sure that everything works in the IDE, I haven't tested that for a long time.
but you can set the path there in the console like this:
export PATH=$PATH:/opt/gowin/IDE/bin/

then you can build the bitfile with:
(cd Output/Mecanix/Gateware ; make clean all)
ls Output/Mecanix/Gateware/impl/pnr/project.fs

EDIT: the config i build is only for testing, serial port will not work for LinuxCNC,
if you want to run LinuxCNC you need SPI (raspberry) or UDP (W5500 / UDP2SPI-Bridge)
Last edit: 31 Jul 2024 19:01 by meister.
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01 Aug 2024 13:41 #306616 by Mecanix

[code][code]EDIT: the config i build is only for testing, serial port will not work for LinuxCNC,
if you want to run LinuxCNC you need SPI (raspberry) or UDP (W5500 / UDP2SPI-Bridge)
[/code][/code]

Everything set-up & synthetizing-wise is working flawlessly. Said it before and I'll say it again; pretty EPIC work you've done for us   

I took onto your advice and stopped by my local gizmo shop to pick a W5500 Lite. Inserting a visual of my benchtop hardware set-up for inspiration and good luck! 



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01 Aug 2024 13:52 - 01 Aug 2024 13:55 #306619 by Mecanix
Note: Prolly not going to work, or be super-reliable with those inductive antena jumper leads lol. Good enough for testing anyway. If this all works out I'll amend the dev board and swing on a wiznet w5500 part with the magnetics, route cross-talk outta of it, add the highspeed opto and level shifters for ins & outs. Guessing the SPI is plenty sufficient for comm and so no need for the realteck gigabit, methink.

I'll keep you updated. Thanks again, meister.
Last edit: 01 Aug 2024 13:55 by Mecanix.
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01 Aug 2024 14:19 #306623 by meister
thank you, you make me embarrassed :)

i am not yet satisfied with the W5500, better not to plan for it, there are packet losses and i have no idea why, it can't be because of the cables as i have test setups without them.

At the moment a UDP2SPI bridge (esp32) is still the best solution.

In principle, you could also programme the FPGA via an esp32 (JTAG or SPI flash), but you would have to adapt the firmware first.

I also have a working RMII interface, but so far I have only been able to get it to run on a TangPrimer20K (with gowin toolchain) and even there I still have a few problems.

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01 Aug 2024 15:02 #306625 by Mecanix

i am not yet satisfied with the W5500, better not to plan for it, there are packet losses and i have no idea why, it can't be because of the cables as i have test setups without them.

I also have a working RMII interface, but so far I have only been able to get it to run on a TangPrimer20K (with gowin toolchain) and even there I still have a few problems.

Are you sure about that w5500 pkts losses issue? Perhaps my silly jumper leads are less inductive/destructive than anticipated, I don't know. To me the losses are within 'functional specs' when a brutal ping beat-up is applied (see visual). Not 0% perfect ofc, but then no interfaces are perfect under that stress, to my limited knowledge mind you. 

The RMII reference design is an excellent one indeed. Not easy to implement though, you have my respect. 


 

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01 Aug 2024 15:33 #306628 by Mecanix
Comparison added for the sake of having something to compare too. Nothing scientific ofc, however goes to show. Here's me brutalizing the gateway the same way, yet here we are talking, lket alone streaming 4k vids, dwloading gigabytes of data from int'l servers. 

I'm not an network expert but, this W5500-over-RIO seems to be bullet proof!! Fairly impressed already. 

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01 Aug 2024 15:33 - 01 Aug 2024 15:35 #306629 by meister
the rmii code is not mine, unfortunately my knowledge of verilog is not sufficient for that, i have only adapted it to rio

github.com/sipeed/TangPrimer-20K-example...Ethernet/verilog_UDP

you can run the rio-test tool to see the timeouts:
PYTHONPATH=. bin/rio-test riocore/configs/MecanixDev/config-test.json 192.168.10.194:2390

all in all, it works quite well with the w5500, but with the esp32 I get no timeouts at all

EDIT: the ping is completely handled inside the W5500, so it's not a good test
Last edit: 01 Aug 2024 15:35 by meister.
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01 Aug 2024 15:52 #306632 by Mecanix
hmm, ok fair enough. I'm no expert and so glad you are. I'm quite grateful I can actually get step pulses out to the oscope and comm with Lcnc already. Pretty cool. Guess fine-tuning this comm reliably will require some significant effort (knowledge?). I'll have a look at the RMII and Esp32 solutions when time allows, and see what comes out. Expect stupid/clueless questions coming your way soon enough though!!

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01 Aug 2024 17:34 #306642 by Mecanix
@meister

Late on and I got it to work. However and as you've pointed out, the comm needs fine tuning! Can I bother you once more and ask for a detailed hardware desc for the ESP32 you've mentioned? Is there a UDP module in particular you'd like us to use and dev around? I'm also happy to get a RMII breakerboard as a second option. Both would be ideal though. All-in-all it's working well. Congrats!!

Visual of the w5500 output:

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