SSI absolute encoders and analog servos

looks basically OK

As a side note all the SSI encoders ( if they have identical timing ) should be using the same timer
this wont cause any issues but wastes timers

What is the time scale of the DPLL phase error plot?

If I had to guess the problem I would guess that the hosts PCI clock is not 33.3 MHz so the DPLL base frequency is not correct

Oh, ok I will change this. I will check time scale tomorrow. How can I check actual PCI clock of system?

Tero

4000 samples at 1kHz

Tero

OK but what i really need is halscopes time/division setting

OK so about 10 Hz (a 1% error)

This does expose a weakness of the DPLL for the 5I25 and 5I24 that depend on the PCI clock for timing
Some Motherboards do not set the PCI clock close enough to 33.33 MHz to allow the DPLL to lock

Ultimately this should probably be fixed in the hm2 driver by a clock calibration phase, but for now
to use that motherboard you will have to tweak the DPLL base frequency

I would try +1% and -1% first

setp hm2_5i25.0.dpll.base-frequency-khz 1.01

and

setp hm2_5i25.0.dpll.base-frequency-khz 0.99

and see if either gives you a lock

once you have a lock, you can tweak the number to get the smallest absolute offset
of the average phase error