Flash a XC6SLX9 dev board as a 7i90HD

Thats what you will get if you did not add your new card file to the sources list

PCW wrote: Thats what you will get if you did not add your new card file to the sources list

In TopGCSPIHostMot2.vhd at the beginning ? Or in ISE tick boxes ?

The proper card type (you should really use your own name here) and pinout file must be included in the top level file

In addition, any source file used must be added to the project
(right click in file window and add if they are not listed)

PCW, a bit off topic.
but i was wondering... there's no PCI setup/hold timing constraints in the 5i25.ucf or elsewhere. how do you get away without them?

They should be there, my oversight, though its not really possible to violate the
PCI specs rather generous 7 ns setup, 0 ns hold and 11 ns output offset specs at 33 MHz with one wait state.

Also the Async TRDY, DEVSEL and STOP signals should have pad-pad times
(more likely to be an issue at 66MHz)

I will look into adding these

thank you for clarification! have to study your PCI implementation... my PCI core implementation attempt effortlessly miss that generous 11ns output offset budget by 3ns on AD pins. among other less severe violations