PCW wrote: You cannot change the EEPROM pin assignment if you expect the FPGA to load its configuration on startup (the configuration SPI pins are always on the same FPGA pins)
SO how can i put a config file ? in the FPGA itself ?
PCW wrote: You will also need a clock, the 7I90 assumes 50 MHz
There is a clock onboard, it's a 50Mhz on pin 55 (it's a 25Mhz on the schematics)
so i have to modify this line :
Code:
NET "CLK" LOC ="P50" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
to this :
Code:
NET "CLK" LOC ="P55" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
I'm downloading the ISE 13.4 to compile the firmware.
