ColorCNC Colorlight 5A-75E/5A-75B as FPGA controller board

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4 years 5 months ago - 4 years 5 months ago #243468 by muvideo
Hi,
I'd like to try your implementation on real hardware.
Maybe I lost something but I'm having difficulty to build the firmware.
I have latest Litex on my machine (Ubuntu 20.04 python 3.8.10).
once cloned the branch "envoders" from your repository in my home directory
then
Code:
cd LiteX-CNC/ python3 -m firmware examples/5a-75e-hello-gpio.json

It fails with this message:
Code:
  File "/home/fabio/LiteX-CNC/firmware/soc.py", line 86, in __init__     super().__init__(config)   File "/home/fabio/LiteX-CNC/firmware/boards/colorlight.py", line 66, in __init__     super().__init__("5a-75b", "6.0", config, sys_clk_freq)   File "/home/fabio/litex/litex/litex/soc/integration/soc_core.py", line 386, in __init__     SoCCore.__init__(self, *args, **kwargs)   File "/home/fabio/litex/litex/litex/soc/integration/soc_core.py", line 121, in __init__     LiteXSoC.__init__(self, platform, clk_freq,   File "/home/fabio/litex/litex/litex/soc/integration/soc.py", line 747, in __init__     self.logger.info("FPGA device : {}.".format(platform.device)) AttributeError: 'str' object has no attribute 'device'

So I'm making some mistake, what is the supposed way to build the firmware?
Thanks.
Last edit: 4 years 5 months ago by muvideo.
The following user(s) said Thank You: TOLP2

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4 years 5 months ago - 4 years 5 months ago #243573 by TOLP2
Thanks for trying it out. You didn't do anything wrong, you found a bug in initializing the colorlight-board. I fixed the problem I would like to ask you to please test again.

The supported board types are:
  • 5A-75B:
    • version 6.1:
      Code:
      "baseclass": "firmware.boards.ColorLight_5A_75B_V6_1"
    • version 7.0:
      Code:
      "baseclass": "firmware.boards.ColorLight_5A_75B_V7_0"
    • version 8.0:
      Code:
      "baseclass": "firmware.boards.ColorLight_5A_75B_V8_0"
  • 5A-75E:
    • version 6.0 (can also be used for version 8.0):
      Code:
      "baseclass": "firmware.boards.ColorLight_5A_75E_V6_0"
    • version 7.1:
      Code:
      "baseclass": "firmware.boards.ColorLight_5A_75E_V7_1"
  • RV901T: 
    Code:
    "baseclass": "firmware.boards.RV901T"
If you find any trouble getting the firmware running, please let me know here and I will explain or fix. Also, I started to work on the wiki. I will give a shout when it is finished.
Last edit: 4 years 5 months ago by TOLP2.
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4 years 5 months ago #243574 by muvideo
Hello,
did you commit any changes on your LiteX-CNC repo?
I'm not seeing anything new there.
What should I modify to make the firmware build?
Thanks

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4 years 5 months ago #243576 by TOLP2
Sorry, the commit was pushed just now ...

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4 years 5 months ago - 4 years 5 months ago #243577 by muvideo
Wonderful, thanks, I confirm now it's working.
If I understand correctly, now it is generating the verilog file but
is not starting the generation of svf binary file.
Is it possible to have the binary generated trough
yosys/nextpnr directly like for litex template files?
Thanks,
Fabio

Edit:
Set builder.build(run=True) in __main__.py line 33
Tried also to run builder scripts generated by Litex
but I'm getting this error:

Code:
... Successfully finished Verilog frontend. 3.3. Executing HIERARCHY pass (managing design hierarchy). 3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\colorlight_5a_75e'. Generating RTLIL representation for module `\colorlight_5a_75e'. 3.4.1. Analyzing design hierarchy.. Top module:  \colorlight_5a_75e ERROR: Module `\IDDR2' referenced in module `\colorlight_5a_75e' in cell `\IDDR2_4' is not part of the design. Traceback (most recent call last):   File "/usr/lib/python3.8/runpy.py", line 194, in _run_module_as_main     return _run_code(code, main_globals, None, ...  
Last edit: 4 years 5 months ago by muvideo.

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4 years 5 months ago #243611 by TOLP2
Small mistake, hard to debug. It is solved and pushed to the repo.

On the main branch the Colorlight FPGA's did work. When modifying the code to support more types of boards I made a typo  in the typhe of Ethernet PHY used on the Colorlight cards (ECP5). As a result, the buffer of the etehrnet packages was written to the wrong addresses. I did test the complete toolchain now from creating the firmware until compiling it to a bit-file.

As for your request to automatically built the bit-file, I'll put it on the board for the next iteration. Will implement it as a command-line argument, as not all users will have the complete toolchain installed within their environment (the ECP5 toolchain is the exception).

 
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