New project, litehm2: a hostmot2 port to linsn rv901t

The board name in the conf file is for building the firmware, the developer has a branch for another board that uses a different brand of FPGA, the tools used for the build will depend on the FPGA brand used. The conf file defines the configuration you want for your board, Linuxcnc does not use it.

The actual board name presented to Linuxcnc is buried within the vdhl files.

Towards the end of the gitub README
TODOs
add more boards
use InM and OutM instead of GPIO
make pncconf and mesact work out of the box

Which looking at the latest commits there has been no mention of.

So for the time being one would expect a user to start with the developer supplied ini & hal files and modify to suit.

The base name used in LinuxCNCs hal pins/parameters/functions
is a bit more involved. On Ethernet cards, the Ethernet card name
(LITEHM2) is used by the driver to create the base name.
(hm2_lite in this case)

 

So not quite the same when using an EPP or SPI interface ?
Cos I’ve only added the 4 character card name eg “9d60” when I’ve been making bit files for the dev boards I’ve been experimenting with. It’s been a good few months since I’ve done that.

Yeah, Ethernet cards are different, they have an up to 16
character name stored in EEPROM. On Ethernet cards the
driver uses the card name from the EEPROM rather than
the one in the low level firmware.

Ahhh I see now, thanks for that. Haven't really looked at the ethernet code (working out the ssreial code for the 7i90 was a journey in itself, but the ethernet code would mean also coming familiar with the etherent chip), for the price of trying to implement that at home it doesn't make sense.

I really I didn't swap from an electronics trade to carpentry when I was a teenager......but being outside and using my hands was a greater calling.

Hi all.
In the end, I was able to launch the boards, what were the nuances:
1. the boards were modified on the recommendation of Ilya Kubakin, there was a nuance with a resistor that caught a track that needed to be cut. I fixed it and checked it several times.
2. why I went to look at the soldering, because the buffers got very hot. and on the firmware from the section called rv901t... they didn’t work, or rather 2 channels worked, after fixing the board, the buffers continued to heat up.
3.Then I went the other way, I found Ilya’s config and installed it on the board, in the config the description of the ports for connectors J600 and J601 was quite clear. This helped to check all the input and output ports, the encoders work very strangely, I will look into it.
4 I need training in creating my own config, I need point Z from encoders, Ilya doesn’t have this written down, only phase A and B
5. linuxcnc запускается после перезагрузки платы и то с 5го раза, не понимаю с чем связано, возможно с тем, что плата не умеет делать перезагрузку без выключения питания. после выключения linuxcnc, запуск происходит в хаотичном порядке, может запустить сразу, может с 10го.
6. . I like the idea of splitting 2 connectors, one for input, the other for output. However, I want to make switching boards, and for example, version 5A-75E with separate groups.

Please contact me on telegram channel "LinuxCNC". I will help you as much as I can.

Hi all.

i have problem.

error mesaflash
linux reports an error: 
Checking file ... OK
   File type: BIT file
Error: BootSector is invalid


I have two files. 
1. tuxcnc-mod.bit
forum.linuxcnc.org/27-driver-boards/4773...901t?start=80#274777

2. my.bit 
I make the file myself using VM from IlyaKw

I load the first file using jtag.
After which I can write --write tuxcnc-mod.bit
I can --fix-boot-block
I can --fallback
mesaflash --device 7I92 --addr 192.168.1.121 --fix-boot-block --fallback --write tuxcnc-mod.bit
mesaflash --device 7I92 --addr 192.168.1.121 --write tuxcnc-mod.bit
Everything is fine and there are no errors.

I can even load my second file mesaflash --device 7I92 --addr 192.168.1.121 --write my.bit
The program is loading successfully
But after rebooting I can't load any firmware and I get the message
Checking file ... OK
   File type: BIT file
Error: BootSector is invalid

These commands do not work.
--write tuxcnc-mod.bit I --fix-boot-block --fallback

Me and I have to use jtag again

The problem is not very serious.

But I want to understand the fallback mechanism
Why do different files behave differently.

Apparently I am making a bad file that works via jtag but does not work with mesaflash.

Please tell me more about fallback

Might be this:
(from the 7I92 manual)

The configuration utilities expect standard FPGA bitfiles without any multiboot features
enabled. If multiboot FPGA files are loaded they will likely cause a configuration failure.

Might also be an issue with the flash chip size detection.
 

hi all.
i have problem.


(litexcnc) vasya@debian:~/litehm2$ make
make -f Makefile.target TARGET=rv901t_4out__3stepgen_2enc_1pwm
make[1]: Entering directory '/home/vasya/litehm2'
dd if=/dev/zero of=build/rv901t_4out__3stepgen_2enc_1pwm/firmware/firmware.bin bs=32k count=1
1+0 records in
1+0 records out
32768 bytes (33 kB, 32 KiB) copied, 0.00169724 s, 19.3 MB/s
dd if=/dev/zero of=build/rv901t_4out__3stepgen_2enc_1pwm/firmware/loader.bin bs=4k count=1
1+0 records in
1+0 records out
4096 bytes (4.1 kB, 4.0 KiB) copied, 0.000610246 s, 6.7 MB/s
./litehm2.py --builddir=build/rv901t_4out__3stepgen_2enc_1pwm --config=configs/rv901t_4out__3stepgen_2enc_1pwm.conf
INFO:S6PLL:Creating S6PLL, speedgrade -2.
INFO:S6PLL:Registering Single Ended ClkIn of 25.00MHz.
INFO:S6PLL:Creating ClkOut0 sys of 80.00MHz (+-10000.00ppm).
INFO:S6PLL:Creating ClkOut1 fast of 200.00MHz (+-10000.00ppm).
Traceback (most recent call last):
  File "/home/vasya/litehm2/./litehm2.py", line 201, in <module>
    main()
  File "/home/vasya/litehm2/./litehm2.py", line 194, in main
    soc = LiteHM2(ip_address=args.ip_address,
          ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/home/vasya/litehm2/./litehm2.py", line 94, in __init__
    main_ram_init = get_mem_data(builddir + "/firmware/firmware.bin",
                    ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
TypeError: get_mem_data() got an unexpected keyword argument 'data_width'
make[1]: *** [Makefile.target:10: litehm2] Error 1
make[1]: Leaving directory '/home/vasya/litehm2'
make: *** [Makefile:8: bitstreams/rv901t_4out__3stepgen_2enc_1pwm.bit] Error 2
(litexcnc) vasya@debian:~/litehm2$