Where to start with Mesa 7i92 + 7i85S

Jrjones
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10 years 9 months ago #68074 by Jrjones

Replied by Jrjones on topic Where to start with Mesa 7i92 + 7i85S

Thanks for the bit file cncbasher.
It appears to have loaded correctly, I did load it into the fallback area as PCW suggested in case it didn't work.

Code:

Configuration Name: HOSTMOT2

General configuration information:

  BoardName : MESA7I92
  FPGA Size: 9 KGates
  FPGA Pins: 144
  Number of IO Ports: 2
  Width of one I/O port: 17
  Clock Low frequency: 100.0000 MHz
  Clock High frequency: 200.0000 MHz
  IDROM Type: 3
  Instance Stride 0: 4
  Instance Stride 1: 64
  Register Stride 0: 256
  Register Stride 1: 256

Modules in configuration:

  Module: WatchDog
  There are 1 of WatchDog in configuration
  Version: 0
  Registers: 3
  BaseAddress: 0C00
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: IOPort
  There are 2 of IOPort in configuration
  Version: 0
  Registers: 5
  BaseAddress: 1000
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: MuxedQCount
  There are 8 of MuxedQCount in configuration
  Version: 3
  Registers: 5
  BaseAddress: 3600
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: MuxedQCountSel
  There are 1 of MuxedQCountSel in configuration
  Version: 0
  Registers: 0
  BaseAddress: 0000
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: SSerial
  There are 1 of SSerial in configuration
  Version: 0
  Registers: 6
  BaseAddress: 5B00
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 64 bytes

  Module: PWM
  There are 8 of PWM in configuration
  Version: 0
  Registers: 5
  BaseAddress: 4100
  ClockFrequency: 200.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: LED
  There are 1 of LED in configuration
  Version: 0
  Registers: 1
  BaseAddress: 0200
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

Configuration pin-out:

IO Connections for P2
Pin#  I/O   Pri. func    Sec. func       Chan      Pin func        Pin Dir

 1      0   IOPort       SSerial          0        RXData1         (In)
14      1   IOPort       SSerial          0        TXData1         (Out)
 2      2   IOPort       PWM              3        PWM             (Out)
15      3   IOPort       PWM              3        Dir             (Out)
 3      4   IOPort       PWM              2        PWM             (Out)
16      5   IOPort       PWM              2        Dir             (Out)
 4      6   IOPort       PWM              1        PWM             (Out)
17      7   IOPort       PWM              1        Dir             (Out)
 5      8   IOPort       PWM              0        PWM             (Out)
 6      9   IOPort       PWM              0        Dir             (Out)
 7     10   IOPort       MuxedQCountSel   0        MuxSel0         (Out)
 8     11   IOPort       MuxedQCount      0        MuxQ-A          (In)
 9     12   IOPort       MuxedQCount      0        MuxQ-B          (In)
10     13   IOPort       MuxedQCount      0        MuxQ-IDX        (In)
11     14   IOPort       MuxedQCount      1        MuxQ-A          (In)
12     15   IOPort       MuxedQCount      1        MuxQ-B          (In)
13     16   IOPort       MuxedQCount      1        MuxQ-IDX        (In)

IO Connections for P1
Pin#  I/O   Pri. func    Sec. func       Chan      Pin func        Pin Dir

 1     17   IOPort       SSerial          0        RXData2         (In)
14     18   IOPort       SSerial          0        TXData2         (Out)
 2     19   IOPort       PWM              7        PWM             (Out)
15     20   IOPort       PWM              7        Dir             (Out)
 3     21   IOPort       PWM              6        PWM             (Out)
16     22   IOPort       PWM              6        Dir             (Out)
 4     23   IOPort       PWM              5        PWM             (Out)
17     24   IOPort       PWM              5        Dir             (Out)
 5     25   IOPort       PWM              4        PWM             (Out)
 6     26   IOPort       PWM              4        Dir             (Out)
 7     27   IOPort       MuxedQCountSel   4        MuxSel0         (Out)
 8     28   IOPort       MuxedQCount      2        MuxQ-A          (In)
 9     29   IOPort       MuxedQCount      2        MuxQ-B          (In)
10     30   IOPort       MuxedQCount      2        MuxQ-IDX        (In)
11     31   IOPort       MuxedQCount      3        MuxQ-A          (In)
12     32   IOPort       MuxedQCount      3        MuxQ-B          (In)
13     33   IOPort       MuxedQCount      3        MuxQ-IDX        (In)

So I should be to configure the Dir pin as a second (inverted) complement to the primary PWM pin?

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andypugh
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10 years 9 months ago #68076 by andypugh

Replied by andypugh on topic Where to start with Mesa 7i92 + 7i85S

Jrjones wrote: So I should be to configure the Dir pin as a second (inverted) complement to the primary PWM pin?

Is that what you need?

The 7i85S outputs are in differential pairs, TX0 and /TX0 for example.

The potential output configs for the PWM are here:
linuxcnc.org/docs/2.7/html/man/man9/hostmot2.9.html#pwmgen

But it is possible that the bitfile you have has a special pwmgen.

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PCW
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10 years 9 months ago #68110 by PCW

Replied by PCW on topic Where to start with Mesa 7i92 + 7i85S

The 7i85spx2 config has standard pwmgens. The direction outputs are not useful for the locked antiphase
PWM mode that you need so will not be used with this configuration. As far as has been determined, the
Prototrac drives use a single PWM signal per drive, but the signal is transmitted differentially so requires
a differential pair (2 wires that carry the same PWM signal but with opposite polarities)

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techrat
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10 years 6 months ago #73027 by techrat

Replied by techrat on topic Where to start with Mesa 7i92 + 7i85S

I am attempting to do pretty much the same exact thing as Jrjones except I am using the 5i25/7i85s combination. I was on the fence about starting a new thread or jumping in on this one. In the end, I decided to jump in here as I am at about the same progress point and I think that answers to our respective questions will likely help one another.

Basics:
Same machine/servos/amps that JrJones is using.
5i25/7i85s boards
5i25 installed in PC running LINUXCNC - 2.7.0
7i85 not currently connected to 5i25 (just not connecting until I am sure I am ready)
5i25 flashed with 5i25_7i85spx2.bit downloaded from Mesa Website

OUTPUT FROM mesaflash -verify

Code:

sudo mesaflash --device 5I25 --verify ../configs/hostmot2/5i25_7i85spx2.bit 
Checking file... OK
  File type: BIT file
Boot sector OK
Verifying EEPROM sectors starting from 0x100000...
  |VVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVV
Board configuration verified successfully.

OUTPUT FROM halcmd: show pin

Code:

halcmd: loadrt hm2_pci 
halcmd: show pin
Component Pins:
Owner   Type  Dir         Value  Name
s32   OUT             0  hm2_5i25.0.encoder.00.count
s32   OUT             0  hm2_5i25.0.encoder.00.count-latched
bit   I/O         FALSE  hm2_5i25.0.encoder.00.index-enable
bit   OUT          TRUE  hm2_5i25.0.encoder.00.input-a
bit   OUT          TRUE  hm2_5i25.0.encoder.00.input-b
bit   OUT         FALSE  hm2_5i25.0.encoder.00.input-index
bit   IN          FALSE  hm2_5i25.0.encoder.00.latch-enable
bit   IN          FALSE  hm2_5i25.0.encoder.00.latch-polarity
float OUT             0  hm2_5i25.0.encoder.00.position
float OUT             0  hm2_5i25.0.encoder.00.position-latched
bit   OUT         FALSE  hm2_5i25.0.encoder.00.quad-error
bit   IN          FALSE  hm2_5i25.0.encoder.00.quad-error-enable
s32   OUT             0  hm2_5i25.0.encoder.00.rawcounts
s32   OUT             0  hm2_5i25.0.encoder.00.rawlatch
bit   IN          FALSE  hm2_5i25.0.encoder.00.reset
float OUT             0  hm2_5i25.0.encoder.00.velocity
s32   OUT             0  hm2_5i25.0.encoder.01.count
s32   OUT             0  hm2_5i25.0.encoder.01.count-latched
bit   I/O         FALSE  hm2_5i25.0.encoder.01.index-enable
bit   OUT          TRUE  hm2_5i25.0.encoder.01.input-a
bit   OUT          TRUE  hm2_5i25.0.encoder.01.input-b
bit   OUT         FALSE  hm2_5i25.0.encoder.01.input-index
bit   IN          FALSE  hm2_5i25.0.encoder.01.latch-enable
bit   IN          FALSE  hm2_5i25.0.encoder.01.latch-polarity
float OUT             0  hm2_5i25.0.encoder.01.position
float OUT             0  hm2_5i25.0.encoder.01.position-latched
bit   OUT         FALSE  hm2_5i25.0.encoder.01.quad-error
bit   IN          FALSE  hm2_5i25.0.encoder.01.quad-error-enable
s32   OUT             0  hm2_5i25.0.encoder.01.rawcounts
s32   OUT             0  hm2_5i25.0.encoder.01.rawlatch
bit   IN          FALSE  hm2_5i25.0.encoder.01.reset
float OUT             0  hm2_5i25.0.encoder.01.velocity
s32   OUT             0  hm2_5i25.0.encoder.02.count
s32   OUT             0  hm2_5i25.0.encoder.02.count-latched
bit   I/O         FALSE  hm2_5i25.0.encoder.02.index-enable
bit   OUT          TRUE  hm2_5i25.0.encoder.02.input-a
bit   OUT          TRUE  hm2_5i25.0.encoder.02.input-b
bit   OUT         FALSE  hm2_5i25.0.encoder.02.input-index
bit   IN          FALSE  hm2_5i25.0.encoder.02.latch-enable
bit   IN          FALSE  hm2_5i25.0.encoder.02.latch-polarity
float OUT             0  hm2_5i25.0.encoder.02.position
float OUT             0  hm2_5i25.0.encoder.02.position-latched
bit   OUT         FALSE  hm2_5i25.0.encoder.02.quad-error
bit   IN          FALSE  hm2_5i25.0.encoder.02.quad-error-enable
s32   OUT             0  hm2_5i25.0.encoder.02.rawcounts
s32   OUT             0  hm2_5i25.0.encoder.02.rawlatch
bit   IN          FALSE  hm2_5i25.0.encoder.02.reset
float OUT             0  hm2_5i25.0.encoder.02.velocity
s32   OUT             0  hm2_5i25.0.encoder.03.count
s32   OUT             0  hm2_5i25.0.encoder.03.count-latched
bit   I/O         FALSE  hm2_5i25.0.encoder.03.index-enable
bit   OUT          TRUE  hm2_5i25.0.encoder.03.input-a
bit   OUT          TRUE  hm2_5i25.0.encoder.03.input-b
bit   OUT         FALSE  hm2_5i25.0.encoder.03.input-index
bit   IN          FALSE  hm2_5i25.0.encoder.03.latch-enable
bit   IN          FALSE  hm2_5i25.0.encoder.03.latch-polarity
float OUT             0  hm2_5i25.0.encoder.03.position
float OUT             0  hm2_5i25.0.encoder.03.position-latched
bit   OUT         FALSE  hm2_5i25.0.encoder.03.quad-error
bit   IN          FALSE  hm2_5i25.0.encoder.03.quad-error-enable
s32   OUT             0  hm2_5i25.0.encoder.03.rawcounts
s32   OUT             0  hm2_5i25.0.encoder.03.rawlatch
bit   IN          FALSE  hm2_5i25.0.encoder.03.reset
float OUT             0  hm2_5i25.0.encoder.03.velocity
s32   OUT             0  hm2_5i25.0.encoder.04.count
s32   OUT             0  hm2_5i25.0.encoder.04.count-latched
bit   I/O         FALSE  hm2_5i25.0.encoder.04.index-enable
bit   OUT          TRUE  hm2_5i25.0.encoder.04.input-a
bit   OUT          TRUE  hm2_5i25.0.encoder.04.input-b
bit   OUT         FALSE  hm2_5i25.0.encoder.04.input-index
bit   IN          FALSE  hm2_5i25.0.encoder.04.latch-enable
bit   IN          FALSE  hm2_5i25.0.encoder.04.latch-polarity
float OUT             0  hm2_5i25.0.encoder.04.position
float OUT             0  hm2_5i25.0.encoder.04.position-latched
bit   OUT         FALSE  hm2_5i25.0.encoder.04.quad-error
bit   IN          FALSE  hm2_5i25.0.encoder.04.quad-error-enable
s32   OUT             0  hm2_5i25.0.encoder.04.rawcounts
s32   OUT             0  hm2_5i25.0.encoder.04.rawlatch
bit   IN          FALSE  hm2_5i25.0.encoder.04.reset
float OUT             0  hm2_5i25.0.encoder.04.velocity
s32   OUT             0  hm2_5i25.0.encoder.05.count
s32   OUT             0  hm2_5i25.0.encoder.05.count-latched
bit   I/O         FALSE  hm2_5i25.0.encoder.05.index-enable
bit   OUT          TRUE  hm2_5i25.0.encoder.05.input-a
bit   OUT          TRUE  hm2_5i25.0.encoder.05.input-b
bit   OUT         FALSE  hm2_5i25.0.encoder.05.input-index
bit   IN          FALSE  hm2_5i25.0.encoder.05.latch-enable
bit   IN          FALSE  hm2_5i25.0.encoder.05.latch-polarity
float OUT             0  hm2_5i25.0.encoder.05.position
float OUT             0  hm2_5i25.0.encoder.05.position-latched
bit   OUT         FALSE  hm2_5i25.0.encoder.05.quad-error
bit   IN          FALSE  hm2_5i25.0.encoder.05.quad-error-enable
s32   OUT             0  hm2_5i25.0.encoder.05.rawcounts
s32   OUT             0  hm2_5i25.0.encoder.05.rawlatch
bit   IN          FALSE  hm2_5i25.0.encoder.05.reset
float OUT             0  hm2_5i25.0.encoder.05.velocity
s32   OUT             0  hm2_5i25.0.encoder.06.count
s32   OUT             0  hm2_5i25.0.encoder.06.count-latched
bit   I/O         FALSE  hm2_5i25.0.encoder.06.index-enable
bit   OUT          TRUE  hm2_5i25.0.encoder.06.input-a
bit   OUT          TRUE  hm2_5i25.0.encoder.06.input-b
bit   OUT         FALSE  hm2_5i25.0.encoder.06.input-index
bit   IN          FALSE  hm2_5i25.0.encoder.06.latch-enable
bit   IN          FALSE  hm2_5i25.0.encoder.06.latch-polarity
float OUT             0  hm2_5i25.0.encoder.06.position
float OUT             0  hm2_5i25.0.encoder.06.position-latched
bit   OUT         FALSE  hm2_5i25.0.encoder.06.quad-error
bit   IN          FALSE  hm2_5i25.0.encoder.06.quad-error-enable
s32   OUT             0  hm2_5i25.0.encoder.06.rawcounts
s32   OUT             0  hm2_5i25.0.encoder.06.rawlatch
bit   IN          FALSE  hm2_5i25.0.encoder.06.reset
float OUT             0  hm2_5i25.0.encoder.06.velocity
s32   OUT             0  hm2_5i25.0.encoder.07.count
s32   OUT             0  hm2_5i25.0.encoder.07.count-latched
bit   I/O         FALSE  hm2_5i25.0.encoder.07.index-enable
bit   OUT          TRUE  hm2_5i25.0.encoder.07.input-a
bit   OUT          TRUE  hm2_5i25.0.encoder.07.input-b
bit   OUT         FALSE  hm2_5i25.0.encoder.07.input-index
bit   IN          FALSE  hm2_5i25.0.encoder.07.latch-enable
bit   IN          FALSE  hm2_5i25.0.encoder.07.latch-polarity
float OUT             0  hm2_5i25.0.encoder.07.position
float OUT             0  hm2_5i25.0.encoder.07.position-latched
bit   OUT         FALSE  hm2_5i25.0.encoder.07.quad-error
bit   IN          FALSE  hm2_5i25.0.encoder.07.quad-error-enable
s32   OUT             0  hm2_5i25.0.encoder.07.rawcounts
s32   OUT             0  hm2_5i25.0.encoder.07.rawlatch
bit   IN          FALSE  hm2_5i25.0.encoder.07.reset
float OUT             0  hm2_5i25.0.encoder.07.velocity
u32   IN     0x007F2815  hm2_5i25.0.encoder.muxed-sample-frequency
bit   OUT          TRUE  hm2_5i25.0.gpio.000.in
bit   OUT         FALSE  hm2_5i25.0.gpio.000.in_not
bit   IN          FALSE  hm2_5i25.0.gpio.000.out
bit   OUT          TRUE  hm2_5i25.0.gpio.001.in
bit   OUT         FALSE  hm2_5i25.0.gpio.001.in_not
bit   IN          FALSE  hm2_5i25.0.gpio.001.out
bit   OUT         FALSE  hm2_5i25.0.gpio.002.in
bit   OUT          TRUE  hm2_5i25.0.gpio.002.in_not
bit   OUT         FALSE  hm2_5i25.0.gpio.003.in
bit   OUT          TRUE  hm2_5i25.0.gpio.003.in_not
bit   OUT         FALSE  hm2_5i25.0.gpio.004.in
bit   OUT          TRUE  hm2_5i25.0.gpio.004.in_not
bit   OUT         FALSE  hm2_5i25.0.gpio.005.in
bit   OUT          TRUE  hm2_5i25.0.gpio.005.in_not
bit   OUT         FALSE  hm2_5i25.0.gpio.006.in
bit   OUT          TRUE  hm2_5i25.0.gpio.006.in_not
bit   OUT         FALSE  hm2_5i25.0.gpio.007.in
bit   OUT          TRUE  hm2_5i25.0.gpio.007.in_not
bit   OUT         FALSE  hm2_5i25.0.gpio.008.in
bit   OUT          TRUE  hm2_5i25.0.gpio.008.in_not
bit   OUT         FALSE  hm2_5i25.0.gpio.009.in
bit   OUT          TRUE  hm2_5i25.0.gpio.009.in_not
bit   OUT         FALSE  hm2_5i25.0.gpio.010.in
bit   OUT          TRUE  hm2_5i25.0.gpio.010.in_not
bit   OUT          TRUE  hm2_5i25.0.gpio.011.in
bit   OUT         FALSE  hm2_5i25.0.gpio.011.in_not
bit   OUT          TRUE  hm2_5i25.0.gpio.012.in
bit   OUT         FALSE  hm2_5i25.0.gpio.012.in_not
bit   OUT          TRUE  hm2_5i25.0.gpio.013.in
bit   OUT         FALSE  hm2_5i25.0.gpio.013.in_not
bit   OUT          TRUE  hm2_5i25.0.gpio.014.in
bit   OUT         FALSE  hm2_5i25.0.gpio.014.in_not
bit   OUT          TRUE  hm2_5i25.0.gpio.015.in
bit   OUT         FALSE  hm2_5i25.0.gpio.015.in_not
bit   OUT          TRUE  hm2_5i25.0.gpio.016.in
bit   OUT         FALSE  hm2_5i25.0.gpio.016.in_not
bit   OUT          TRUE  hm2_5i25.0.gpio.017.in
bit   OUT         FALSE  hm2_5i25.0.gpio.017.in_not
bit   IN          FALSE  hm2_5i25.0.gpio.017.out
bit   OUT          TRUE  hm2_5i25.0.gpio.018.in
bit   OUT         FALSE  hm2_5i25.0.gpio.018.in_not
bit   IN          FALSE  hm2_5i25.0.gpio.018.out
bit   OUT         FALSE  hm2_5i25.0.gpio.019.in
bit   OUT          TRUE  hm2_5i25.0.gpio.019.in_not
bit   OUT         FALSE  hm2_5i25.0.gpio.020.in
bit   OUT          TRUE  hm2_5i25.0.gpio.020.in_not
bit   OUT         FALSE  hm2_5i25.0.gpio.021.in
bit   OUT          TRUE  hm2_5i25.0.gpio.021.in_not
bit   OUT         FALSE  hm2_5i25.0.gpio.022.in
bit   OUT          TRUE  hm2_5i25.0.gpio.022.in_not
bit   OUT         FALSE  hm2_5i25.0.gpio.023.in
bit   OUT          TRUE  hm2_5i25.0.gpio.023.in_not
bit   OUT         FALSE  hm2_5i25.0.gpio.024.in
bit   OUT          TRUE  hm2_5i25.0.gpio.024.in_not
bit   OUT         FALSE  hm2_5i25.0.gpio.025.in
bit   OUT          TRUE  hm2_5i25.0.gpio.025.in_not
bit   OUT         FALSE  hm2_5i25.0.gpio.026.in
bit   OUT          TRUE  hm2_5i25.0.gpio.026.in_not
bit   OUT         FALSE  hm2_5i25.0.gpio.027.in
bit   OUT          TRUE  hm2_5i25.0.gpio.027.in_not
bit   OUT          TRUE  hm2_5i25.0.gpio.028.in
bit   OUT         FALSE  hm2_5i25.0.gpio.028.in_not
bit   OUT          TRUE  hm2_5i25.0.gpio.029.in
bit   OUT         FALSE  hm2_5i25.0.gpio.029.in_not
bit   OUT          TRUE  hm2_5i25.0.gpio.030.in
bit   OUT         FALSE  hm2_5i25.0.gpio.030.in_not
bit   OUT          TRUE  hm2_5i25.0.gpio.031.in
bit   OUT         FALSE  hm2_5i25.0.gpio.031.in_not
bit   OUT          TRUE  hm2_5i25.0.gpio.032.in
bit   OUT         FALSE  hm2_5i25.0.gpio.032.in_not
bit   OUT          TRUE  hm2_5i25.0.gpio.033.in
bit   OUT         FALSE  hm2_5i25.0.gpio.033.in_not
bit   IN          FALSE  hm2_5i25.0.led.CR01
bit   IN          FALSE  hm2_5i25.0.led.CR02
bit   IN          FALSE  hm2_5i25.0.pwmgen.00.enable
float IN              0  hm2_5i25.0.pwmgen.00.value
bit   IN          FALSE  hm2_5i25.0.pwmgen.01.enable
float IN              0  hm2_5i25.0.pwmgen.01.value
bit   IN          FALSE  hm2_5i25.0.pwmgen.02.enable
float IN              0  hm2_5i25.0.pwmgen.02.value
bit   IN          FALSE  hm2_5i25.0.pwmgen.03.enable
float IN              0  hm2_5i25.0.pwmgen.03.value
bit   IN          FALSE  hm2_5i25.0.pwmgen.04.enable
float IN              0  hm2_5i25.0.pwmgen.04.value
bit   IN          FALSE  hm2_5i25.0.pwmgen.05.enable
float IN              0  hm2_5i25.0.pwmgen.05.value
bit   IN          FALSE  hm2_5i25.0.pwmgen.06.enable
float IN              0  hm2_5i25.0.pwmgen.06.value
bit   IN          FALSE  hm2_5i25.0.pwmgen.07.enable
float IN              0  hm2_5i25.0.pwmgen.07.value
s32   OUT             0  hm2_5i25.0.read.time
s32   OUT             0  hm2_5i25.0.read_gpio.time
bit   I/O         FALSE  hm2_5i25.0.watchdog.has_bit
s32   OUT             0  hm2_5i25.0.write.time
s32   OUT             0  hm2_5i25.0.write_gpio.time

With that information out of the way, I am unsure of next steps.

It appears that I can use PNCConf to create a configuration but it appears from previous posts in this thread, this would not be useful for what I need to accomplish. Or is the PNCConf only an issue for jrjones as he is using the 7i92 instead of the 5i25?

Also with regard to the differential signal, does a set of pins already exist using the standard 5i25-7i85spx2 firmware/config. i.e. are TX0 and /TX0 the same pwm with opposite polarity?

I did read through the HAL manual and the HOSTMOT2 documentation and have a reasonable grasp of the information presented in these documents. It appears as though most of the basics of what I need to get started are already available through the firmware/config that I downloaded from MESA. I just want to be sure that I am taking the correct steps.

Please advise on the recommended next actions and/or other documentation that I should be reading.

Thanks - Jeff

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PCW
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Moderator

10 years 6 months ago #73033 by PCW

Replied by PCW on topic Where to start with Mesa 7i92 + 7i85S

I suspect you may be better of starting with a generic servo config (say hm2-servo)
and editing the hal file.

The 7I85S outputs differential signals already (this is a hardware feature and cannot be changed)
whether these differential outputs are step+dir, PWM, serial, etc are a function of the firmware

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techrat
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Junior Member

10 years 6 months ago #73056 by techrat

Replied by techrat on topic Where to start with Mesa 7i92 + 7i85S

Looking at the folder created by pncconf here:

Code:

~/linuxcnc/configs/my_LinuxCNC_machine

and keeping in mind the advice to start with the generic servo configuration, it appears as though I could keep all of the files except the my_LinuxCNC_machine.hal and replace that file with the hm2-servo.hal from the samples located at

Code:

/usr/share/doc/linuxcnc/examples/sample-configs/by_interface/mesa/

Is there any reason to replace the .ini file created by pncconf? Or can I just go in and rename the hal file listed in the .ini to match the hm2-servo from the sample folder? If I am better off using one of the generic .ini files from the sample folder, which should I use? There does not seem to be an .ini specific to the 5i25.

I am sure I could scratch and crawl my way through this but if you all don't mind giving me a sanity check on my assumptions along the way, I will appreciate it.

Thanks! Jeff

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Where to start with Mesa 7i92 + 7i85S