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Where to start with Mesa 7i92 + 7i85S

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10 years 9 months ago - 10 years 9 months ago #67997 by andypugh
Replied by andypugh on topic Where to start with Mesa 7i92 + 7i85S
You can't use hm2_eth with the RTAI kernel. You need the preempt-rt kernel.

You should be able to start from step 2 here:
linuxcnc.org/docs/2.7/html/getting-start...th_preempt_rt_kernel

(You basically need to install a new kernel and a different variant of LinuxCNC to match it. But it ought to be fairly straightforward)

Step 6 could be clearer. You can do what it suggests in the Synaptic package manager. (System->Synaptic Package Manager. Then Settings->Repositories: Other Software tab, and the Add button
Or edit//create the /etc/apt/sources.list.d/linuxcnc.list file
Last edit: 10 years 9 months ago by andypugh.

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10 years 9 months ago #68000 by Jrjones
Replied by Jrjones on topic Where to start with Mesa 7i92 + 7i85S
Awesome, I remembered reading about that a few months ago but forgot about it.
I'm slowly getting the hang of this.
Code:
Component Pins: Owner Type Dir Value Name 9 float IN 100 hm2_7i92.0.dpll.01.timer-us 9 float IN 100 hm2_7i92.0.dpll.02.timer-us 9 float IN 100 hm2_7i92.0.dpll.03.timer-us 9 float IN 100 hm2_7i92.0.dpll.04.timer-us 9 float IN -1 hm2_7i92.0.dpll.base-freq-khz 9 u32 OUT 0x00000000 hm2_7i92.0.dpll.ddsize 9 float OUT 0 hm2_7i92.0.dpll.phase-error-us 9 u32 IN 0x00400000 hm2_7i92.0.dpll.plimit 9 u32 OUT 0x00000001 hm2_7i92.0.dpll.prescale 9 u32 IN 0x000007D0 hm2_7i92.0.dpll.time-const 9 s32 OUT 0 hm2_7i92.0.encoder.00.count 9 s32 OUT 0 hm2_7i92.0.encoder.00.count-latched 9 bit I/O FALSE hm2_7i92.0.encoder.00.index-enable 9 bit OUT TRUE hm2_7i92.0.encoder.00.input-a 9 bit OUT TRUE hm2_7i92.0.encoder.00.input-b 9 bit OUT FALSE hm2_7i92.0.encoder.00.input-index 9 bit IN FALSE hm2_7i92.0.encoder.00.latch-enable 9 bit IN FALSE hm2_7i92.0.encoder.00.latch-polarity 9 float OUT 0 hm2_7i92.0.encoder.00.position 9 float OUT 0 hm2_7i92.0.encoder.00.position-latched 9 bit OUT FALSE hm2_7i92.0.encoder.00.quad-error 9 bit IN FALSE hm2_7i92.0.encoder.00.quad-error-enable 9 s32 OUT 0 hm2_7i92.0.encoder.00.rawcounts 9 s32 OUT 0 hm2_7i92.0.encoder.00.rawlatch 9 bit IN FALSE hm2_7i92.0.encoder.00.reset 9 float OUT 0 hm2_7i92.0.encoder.00.velocity 9 u32 IN 0x017D7840 hm2_7i92.0.encoder.sample-frequency 9 bit OUT FALSE hm2_7i92.0.gpio.000.in 9 bit OUT TRUE hm2_7i92.0.gpio.000.in_not 9 bit OUT FALSE hm2_7i92.0.gpio.001.in 9 bit OUT TRUE hm2_7i92.0.gpio.001.in_not 9 bit OUT FALSE hm2_7i92.0.gpio.002.in 9 bit OUT TRUE hm2_7i92.0.gpio.002.in_not 9 bit OUT FALSE hm2_7i92.0.gpio.003.in 9 bit OUT TRUE hm2_7i92.0.gpio.003.in_not 9 bit OUT FALSE hm2_7i92.0.gpio.004.in 9 bit OUT TRUE hm2_7i92.0.gpio.004.in_not 9 bit OUT FALSE hm2_7i92.0.gpio.005.in 9 bit OUT TRUE hm2_7i92.0.gpio.005.in_not 9 bit OUT FALSE hm2_7i92.0.gpio.006.in 9 bit OUT TRUE hm2_7i92.0.gpio.006.in_not 9 bit OUT FALSE hm2_7i92.0.gpio.007.in 9 bit OUT TRUE hm2_7i92.0.gpio.007.in_not 9 bit OUT FALSE hm2_7i92.0.gpio.008.in 9 bit OUT TRUE hm2_7i92.0.gpio.008.in_not 9 bit OUT FALSE hm2_7i92.0.gpio.009.in 9 bit OUT TRUE hm2_7i92.0.gpio.009.in_not 9 bit OUT TRUE hm2_7i92.0.gpio.010.in 9 bit OUT FALSE hm2_7i92.0.gpio.010.in_not 9 bit IN FALSE hm2_7i92.0.gpio.010.out 9 bit OUT TRUE hm2_7i92.0.gpio.011.in 9 bit OUT FALSE hm2_7i92.0.gpio.011.in_not 9 bit IN FALSE hm2_7i92.0.gpio.011.out 9 bit OUT TRUE hm2_7i92.0.gpio.012.in 9 bit OUT FALSE hm2_7i92.0.gpio.012.in_not 9 bit IN FALSE hm2_7i92.0.gpio.012.out 9 bit OUT TRUE hm2_7i92.0.gpio.013.in 9 bit OUT FALSE hm2_7i92.0.gpio.013.in_not 9 bit IN FALSE hm2_7i92.0.gpio.013.out 9 bit OUT TRUE hm2_7i92.0.gpio.014.in 9 bit OUT FALSE hm2_7i92.0.gpio.014.in_not 9 bit OUT TRUE hm2_7i92.0.gpio.015.in 9 bit OUT FALSE hm2_7i92.0.gpio.015.in_not 9 bit OUT TRUE hm2_7i92.0.gpio.016.in 9 bit OUT FALSE hm2_7i92.0.gpio.016.in_not 9 bit OUT TRUE hm2_7i92.0.gpio.017.in 9 bit OUT FALSE hm2_7i92.0.gpio.017.in_not 9 bit IN FALSE hm2_7i92.0.gpio.017.out 9 bit OUT TRUE hm2_7i92.0.gpio.018.in 9 bit OUT FALSE hm2_7i92.0.gpio.018.in_not 9 bit IN FALSE hm2_7i92.0.gpio.018.out 9 bit OUT TRUE hm2_7i92.0.gpio.019.in 9 bit OUT FALSE hm2_7i92.0.gpio.019.in_not 9 bit IN FALSE hm2_7i92.0.gpio.019.out 9 bit OUT TRUE hm2_7i92.0.gpio.020.in 9 bit OUT FALSE hm2_7i92.0.gpio.020.in_not 9 bit IN FALSE hm2_7i92.0.gpio.020.out 9 bit OUT TRUE hm2_7i92.0.gpio.021.in 9 bit OUT FALSE hm2_7i92.0.gpio.021.in_not 9 bit IN FALSE hm2_7i92.0.gpio.021.out 9 bit OUT TRUE hm2_7i92.0.gpio.022.in 9 bit OUT FALSE hm2_7i92.0.gpio.022.in_not 9 bit IN FALSE hm2_7i92.0.gpio.022.out 9 bit OUT TRUE hm2_7i92.0.gpio.023.in 9 bit OUT FALSE hm2_7i92.0.gpio.023.in_not 9 bit IN FALSE hm2_7i92.0.gpio.023.out 9 bit OUT TRUE hm2_7i92.0.gpio.024.in 9 bit OUT FALSE hm2_7i92.0.gpio.024.in_not 9 bit IN FALSE hm2_7i92.0.gpio.024.out 9 bit OUT TRUE hm2_7i92.0.gpio.025.in 9 bit OUT FALSE hm2_7i92.0.gpio.025.in_not 9 bit IN FALSE hm2_7i92.0.gpio.025.out 9 bit OUT TRUE hm2_7i92.0.gpio.026.in 9 bit OUT FALSE hm2_7i92.0.gpio.026.in_not 9 bit IN FALSE hm2_7i92.0.gpio.026.out 9 bit OUT TRUE hm2_7i92.0.gpio.027.in 9 bit OUT FALSE hm2_7i92.0.gpio.027.in_not 9 bit IN FALSE hm2_7i92.0.gpio.027.out 9 bit OUT TRUE hm2_7i92.0.gpio.028.in 9 bit OUT FALSE hm2_7i92.0.gpio.028.in_not 9 bit IN FALSE hm2_7i92.0.gpio.028.out 9 bit OUT TRUE hm2_7i92.0.gpio.029.in 9 bit OUT FALSE hm2_7i92.0.gpio.029.in_not 9 bit IN FALSE hm2_7i92.0.gpio.029.out 9 bit OUT TRUE hm2_7i92.0.gpio.030.in 9 bit OUT FALSE hm2_7i92.0.gpio.030.in_not 9 bit IN FALSE hm2_7i92.0.gpio.030.out 9 bit OUT TRUE hm2_7i92.0.gpio.031.in 9 bit OUT FALSE hm2_7i92.0.gpio.031.in_not 9 bit IN FALSE hm2_7i92.0.gpio.031.out 9 bit OUT TRUE hm2_7i92.0.gpio.032.in 9 bit OUT FALSE hm2_7i92.0.gpio.032.in_not 9 bit IN FALSE hm2_7i92.0.gpio.032.out 9 bit OUT TRUE hm2_7i92.0.gpio.033.in 9 bit OUT FALSE hm2_7i92.0.gpio.033.in_not 9 bit IN FALSE hm2_7i92.0.gpio.033.out 9 bit IN FALSE hm2_7i92.0.led.CR01 9 bit IN FALSE hm2_7i92.0.led.CR02 9 bit IN FALSE hm2_7i92.0.led.CR03 9 bit IN FALSE hm2_7i92.0.led.CR04 9 s32 OUT 0 hm2_7i92.0.read-request.time 9 s32 OUT 0 hm2_7i92.0.read.time 9 bit IN FALSE hm2_7i92.0.stepgen.00.control-type 9 s32 OUT 0 hm2_7i92.0.stepgen.00.counts 9 float OUT 0 hm2_7i92.0.stepgen.00.dbg_err_at_match 9 float OUT 0 hm2_7i92.0.stepgen.00.dbg_ff_vel 9 float OUT 0 hm2_7i92.0.stepgen.00.dbg_pos_minus_prev_cmd 9 float OUT 0 hm2_7i92.0.stepgen.00.dbg_s_to_match 9 s32 OUT 0 hm2_7i92.0.stepgen.00.dbg_step_rate 9 float OUT 0 hm2_7i92.0.stepgen.00.dbg_vel_error 9 bit IN FALSE hm2_7i92.0.stepgen.00.enable 9 float IN 0 hm2_7i92.0.stepgen.00.position-cmd 9 float OUT 0 hm2_7i92.0.stepgen.00.position-fb 9 float IN 0 hm2_7i92.0.stepgen.00.velocity-cmd 9 float OUT 0 hm2_7i92.0.stepgen.00.velocity-fb 9 bit IN FALSE hm2_7i92.0.stepgen.01.control-type 9 s32 OUT 0 hm2_7i92.0.stepgen.01.counts 9 float OUT 0 hm2_7i92.0.stepgen.01.dbg_err_at_match 9 float OUT 0 hm2_7i92.0.stepgen.01.dbg_ff_vel 9 float OUT 0 hm2_7i92.0.stepgen.01.dbg_pos_minus_prev_cmd 9 float OUT 0 hm2_7i92.0.stepgen.01.dbg_s_to_match 9 s32 OUT 0 hm2_7i92.0.stepgen.01.dbg_step_rate 9 float OUT 0 hm2_7i92.0.stepgen.01.dbg_vel_error 9 bit IN FALSE hm2_7i92.0.stepgen.01.enable 9 float IN 0 hm2_7i92.0.stepgen.01.position-cmd 9 float OUT 0 hm2_7i92.0.stepgen.01.position-fb 9 float IN 0 hm2_7i92.0.stepgen.01.velocity-cmd 9 float OUT 0 hm2_7i92.0.stepgen.01.velocity-fb 9 bit IN FALSE hm2_7i92.0.stepgen.02.control-type 9 s32 OUT 0 hm2_7i92.0.stepgen.02.counts 9 float OUT 0 hm2_7i92.0.stepgen.02.dbg_err_at_match 9 float OUT 0 hm2_7i92.0.stepgen.02.dbg_ff_vel 9 float OUT 0 hm2_7i92.0.stepgen.02.dbg_pos_minus_prev_cmd 9 float OUT 0 hm2_7i92.0.stepgen.02.dbg_s_to_match 9 s32 OUT 0 hm2_7i92.0.stepgen.02.dbg_step_rate 9 float OUT 0 hm2_7i92.0.stepgen.02.dbg_vel_error 9 bit IN FALSE hm2_7i92.0.stepgen.02.enable 9 float IN 0 hm2_7i92.0.stepgen.02.position-cmd 9 float OUT 0 hm2_7i92.0.stepgen.02.position-fb 9 float IN 0 hm2_7i92.0.stepgen.02.velocity-cmd 9 float OUT 0 hm2_7i92.0.stepgen.02.velocity-fb 9 bit IN FALSE hm2_7i92.0.stepgen.03.control-type 9 s32 OUT 0 hm2_7i92.0.stepgen.03.counts 9 float OUT 0 hm2_7i92.0.stepgen.03.dbg_err_at_match 9 float OUT 0 hm2_7i92.0.stepgen.03.dbg_ff_vel 9 float OUT 0 hm2_7i92.0.stepgen.03.dbg_pos_minus_prev_cmd 9 float OUT 0 hm2_7i92.0.stepgen.03.dbg_s_to_match 9 s32 OUT 0 hm2_7i92.0.stepgen.03.dbg_step_rate 9 float OUT 0 hm2_7i92.0.stepgen.03.dbg_vel_error 9 bit IN FALSE hm2_7i92.0.stepgen.03.enable 9 float IN 0 hm2_7i92.0.stepgen.03.position-cmd 9 float OUT 0 hm2_7i92.0.stepgen.03.position-fb 9 float IN 0 hm2_7i92.0.stepgen.03.velocity-cmd 9 float OUT 0 hm2_7i92.0.stepgen.03.velocity-fb 9 bit IN FALSE hm2_7i92.0.stepgen.04.control-type 9 s32 OUT 0 hm2_7i92.0.stepgen.04.counts 9 float OUT 0 hm2_7i92.0.stepgen.04.dbg_err_at_match 9 float OUT 0 hm2_7i92.0.stepgen.04.dbg_ff_vel 9 float OUT 0 hm2_7i92.0.stepgen.04.dbg_pos_minus_prev_cmd 9 float OUT 0 hm2_7i92.0.stepgen.04.dbg_s_to_match 9 s32 OUT 0 hm2_7i92.0.stepgen.04.dbg_step_rate 9 float OUT 0 hm2_7i92.0.stepgen.04.dbg_vel_error 9 bit IN FALSE hm2_7i92.0.stepgen.04.enable 9 float IN 0 hm2_7i92.0.stepgen.04.position-cmd 9 float OUT 0 hm2_7i92.0.stepgen.04.position-fb 9 float IN 0 hm2_7i92.0.stepgen.04.velocity-cmd 9 float OUT 0 hm2_7i92.0.stepgen.04.velocity-fb 9 s32 IN -1 hm2_7i92.0.stepgen.timer-number 9 bit I/O FALSE hm2_7i92.0.watchdog.has_bit 9 s32 OUT 0 hm2_7i92.0.write.time

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10 years 9 months ago #68002 by PCW
Replied by PCW on topic Where to start with Mesa 7i92 + 7i85S
You probably want this firmware:
7i92_7i85sx2D.bit

which you fetch from mesa and install with mesaflash

sudo apt-get install mesaflash

mesaflash --device 7i92 --write 7i92_7i85sx2D.bit (write the 7I92 flash memory with 7I85S firmware)
mesaflash --device 7i92 --reload (load the FPGA with the new firmware)
mesaflash --device 7i92 --readhmid (read out the current pinout/modules)

(I think mesaflash will use the default 192.168.1.121 IP address if not specified,
if not or if you changed the 7I92s IP address, you need to add the address to the mesaflash command line)

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10 years 9 months ago #68012 by andypugh
Replied by andypugh on topic Where to start with Mesa 7i92 + 7i85S

Jrjones wrote:

Code:
Component Pins: Owner Type Dir Value Name 9 float IN 100 hm2_7i92.0.dpll.01.timer-us 9 float IN 100 hm2_7i92.0.dpll.02.timer-us 9 float IN 100 hm2_7i92.0.dpll.03.timer-us 9 float IN 100 hm2_7i92.0.dpll.04.timer-us 9 float IN -1 hm2_7i92.0.dpll.base-freq-khz 9 u32 OUT 0x00000000 hm2_7i92.0.dpll.ddsize 9 float OUT 0 hm2_7i92.0.dpll.phase-error-us 9 u32 IN 0x00400000 hm2_7i92.0.dpll.plimit 9 u32 OUT 0x00000001 hm2_7i92.0.dpll.prescale 9 u32 IN 0x000007D0 hm2_7i92.0.dpll.time-const 9 s32 OUT 0 hm2_7i92.0.encoder.00.count ...


So, if you create a 5i25 configuration as a way to get the right file structure, you can then go through the INI and HAL files changing the pin names to suit the ones from the list. You may also need to use the "show param" command to get the HAL parameters (various settings that don't change during operation).

As PCW said, getting a bitfile to suit your application might be necessary.

There should be a listing somewhere of how the Mesa functions are mapped to the hardware pins on the 7i92. This is in dmesg with RTAI, but I don't know where it ends up with rt-preempt.

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10 years 9 months ago - 10 years 9 months ago #68021 by PCW
Replied by PCW on topic Where to start with Mesa 7i92 + 7i85S
The uspace version of linuxcnc will print the pinout in the terminal if
linuxcnc is launched from a terminal, not sure if its logged anywhere else

Thats why I suggested:
mesaflash --device 7i92 --readhmid
Since it will print out a formatted pinout (same as a .pin file)
Last edit: 10 years 9 months ago by PCW.

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10 years 9 months ago - 10 years 9 months ago #68032 by Jrjones
Replied by Jrjones on topic Where to start with Mesa 7i92 + 7i85S
Ok, I've got the 7i92_7i85sx2D.bit firmware flashed to the 7i92.
The readhmid command gives me this output, which looks right from the 7i85S documentation.
Code:
Configuration Name: HOSTMOT2 General configuration information: BoardName : MESA7I92 FPGA Size: 9 KGates FPGA Pins: 144 Number of IO Ports: 2 Width of one I/O port: 17 Clock Low frequency: 100.0000 MHz Clock High frequency: 200.0000 MHz IDROM Type: 3 Instance Stride 0: 4 Instance Stride 1: 64 Register Stride 0: 256 Register Stride 1: 256 Modules in configuration: Module: DPLL There are 1 of DPLL in configuration Version: 0 Registers: 7 BaseAddress: 7000 ClockFrequency: 100.000 MHz Register Stride: 256 bytes Instance Stride: 4 bytes Module: WatchDog There are 1 of WatchDog in configuration Version: 0 Registers: 3 BaseAddress: 0C00 ClockFrequency: 100.000 MHz Register Stride: 256 bytes Instance Stride: 4 bytes Module: IOPort There are 2 of IOPort in configuration Version: 0 Registers: 5 BaseAddress: 1000 ClockFrequency: 100.000 MHz Register Stride: 256 bytes Instance Stride: 4 bytes Module: MuxedQCount There are 8 of MuxedQCount in configuration Version: 3 Registers: 5 BaseAddress: 3500 ClockFrequency: 100.000 MHz Register Stride: 256 bytes Instance Stride: 4 bytes Module: MuxedQCountSel There are 1 of MuxedQCountSel in configuration Version: 0 Registers: 0 BaseAddress: 0000 ClockFrequency: 100.000 MHz Register Stride: 256 bytes Instance Stride: 4 bytes Module: SSerial There are 1 of SSerial in configuration Version: 0 Registers: 6 BaseAddress: 5A00 ClockFrequency: 100.000 MHz Register Stride: 256 bytes Instance Stride: 64 bytes Module: StepGen There are 8 of StepGen in configuration Version: 2 Registers: 10 BaseAddress: 2000 ClockFrequency: 100.000 MHz Register Stride: 256 bytes Instance Stride: 4 bytes Module: LED There are 1 of LED in configuration Version: 0 Registers: 1 BaseAddress: 0200 ClockFrequency: 100.000 MHz Register Stride: 256 bytes Instance Stride: 4 bytes Configuration pin-out: IO Connections for P2 Pin# I/O Pri. func Sec. func Chan Pin func Pin Dir 1 0 IOPort SSerial 0 RXData1 (In) 14 1 IOPort SSerial 0 TXData1 (Out) 2 2 IOPort StepGen 3 Step/Table1 (Out) 15 3 IOPort StepGen 3 Dir/Table2 (Out) 3 4 IOPort StepGen 2 Step/Table1 (Out) 16 5 IOPort StepGen 2 Dir/Table2 (Out) 4 6 IOPort StepGen 1 Step/Table1 (Out) 17 7 IOPort StepGen 1 Dir/Table2 (Out) 5 8 IOPort StepGen 0 Step/Table1 (Out) 6 9 IOPort StepGen 0 Dir/Table2 (Out) 7 10 IOPort MuxedQCountSel 0 MuxSel0 (Out) 8 11 IOPort MuxedQCount 0 MuxQ-A (In) 9 12 IOPort MuxedQCount 0 MuxQ-B (In) 10 13 IOPort MuxedQCount 0 MuxQ-IDX (In) 11 14 IOPort MuxedQCount 1 MuxQ-A (In) 12 15 IOPort MuxedQCount 1 MuxQ-B (In) 13 16 IOPort MuxedQCount 1 MuxQ-IDX (In) IO Connections for P1 Pin# I/O Pri. func Sec. func Chan Pin func Pin Dir 1 17 IOPort SSerial 0 RXData2 (In) 14 18 IOPort SSerial 0 TXData2 (Out) 2 19 IOPort StepGen 7 Step/Table1 (Out) 15 20 IOPort StepGen 7 Dir/Table2 (Out) 3 21 IOPort StepGen 6 Step/Table1 (Out) 16 22 IOPort StepGen 6 Dir/Table2 (Out) 4 23 IOPort StepGen 5 Step/Table1 (Out) 17 24 IOPort StepGen 5 Dir/Table2 (Out) 5 25 IOPort StepGen 4 Step/Table1 (Out) 6 26 IOPort StepGen 4 Dir/Table2 (Out) 7 27 IOPort MuxedQCountSel 4 MuxSel0 (Out) 8 28 IOPort MuxedQCount 2 MuxQ-A (In) 9 29 IOPort MuxedQCount 2 MuxQ-B (In) 10 30 IOPort MuxedQCount 2 MuxQ-IDX (In) 11 31 IOPort MuxedQCount 3 MuxQ-A (In) 12 32 IOPort MuxedQCount 3 MuxQ-B (In) 13 33 IOPort MuxedQCount 3 MuxQ-IDX (In)

I'm a little confused how to configure a 5i25, since the 7i85S doesn't appear under the firmware list, and none of the options let me select 6 PWM generators and 3 encoders.
As an aside, is it a problem that the machine doesn't have any home/limit switches? With the Prototrak software, you manually moved the mill to a position and set that as home.
Last edit: 10 years 9 months ago by Jrjones.

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