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Created .mod file

#define MAX_MSG_LEN 16
#define DEBUG 3

static const hm2_modbus_chan_descriptor_t channels[] = {
    {HAL_S32,     6,   0x000,  1,"write"},
    {HAL_S32,     3,   0x100,  1,"read"},
};

loading in .hal file:
.
.
.
addf pid.z.do-pid-calcs       servo-thread
addf pid.s.do-pid-calcs       servo-thread
addf [HMOT](CARD0).write         servo-thread
setp [HMOT](CARD0).dpll.01.timer-us -50
setp [HMOT](CARD0).stepgen.timer-number 1

loadrt my-vfd ports=hm2_7i96s.0.pktuart.0
addf my-vfd.00 servo-thread

# external output signals


# external input signals

# --- MAX-HOME-Z ---
net max-home-z     <=  [HMOT](CARD0).inm.00.input-00-not
.
.
.
Output:
.
.

WAIT_FOR_DATA_FRAME - rxmode = 16000F0C
 1002 TIMEOUT_RESET 3
START txstaus = 00001460 rxstatus = 16000F0C
building packet 6 0 start pin 0
building packet 3 100 start pin 1
Sending to hm2_7i96s.0.pktuart.0 8 bytes 01 03 01 0000 01 85 F6
WAIT_FOR_SENDBEGIN RX 1460 TX 16000F0C
WAIT_FOR_SEND_COMPLETE RX 16000F0C TX 2014E0
.
.
.
While the oszi is still showing a constant 5Volts





 

Thank you for the reply and for the chart! Navigating Mesa's selection for a novice is very confusing.

HH

I completely understand, but you might be surprised what you can find used for that price. Take this one on Ebay for example.
www.ebay.com/itm/256470069304
It is only priced at $2500 and looks like it has a tool changer. (Although the vacuum pump for part hold down would cost extra.)

G0G53Z148 wrote:

Bekommt man noch ein 2.8.xx version zum download?
 

Moin
schau mal hier , da gibt es noch ältere Versionen.

Gruß Fritz

I would try creating a .mod file and doing an actual test

Solved

Hi,

I think I'm having a similar issue with Bosch/Rexroth IndraDrive Cs and get the same SAFEOP failure even without configpdos. These drives have EoE as well so I'm going to try your fix or even to setup the actual EoE so I can access the drives with the drive utility. Did you ever find a root cause for this?

Thanks Giovanni
I'll try it next time, put it in with a long fork and a mask on
Juergen

Hi nmsk,

In researching a similar issue I'm having I ran across this post:

forum.linuxcnc.org/ethercat/51505-new-hardware-trouble

Does your drive support EoE?  If so, this may be a fix as well although I don't know the root cause has been identified.

 

Now in the shop I retrived the .vhd File used to generate the bitfile

library IEEE;
use IEEE.std_logic_1164.all;  -- defines std_logic types
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
--    * GNU General Public License (GPL), version 2.0 or later
--    * 3-clause BSD License
--
--
-- The GNU GPL License:
--
--     This program is free software; you can redistribute it and/or modify
--     it under the terms of the GNU General Public License as published by
--     the Free Software Foundation; either version 2 of the License, or
--     (at your option) any later version.
--
--     This program is distributed in the hope that it will be useful,
--     but WITHOUT ANY WARRANTY; without even the implied warranty of
--     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--     GNU General Public License for more details.
--
--     You should have received a copy of the GNU General Public License
--     along with this program; if not, write to the Free Software
--     Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
--
--
-- The 3-clause BSD License:
--
--     Redistribution and use in source and binary forms, with or without
--     modification, are permitted provided that the following conditions
--     are met:
--
--   * Redistributions of source code must retain the above copyright
--     notice, this list of conditions and the following disclaimer.
--
--   * Redistributions in binary form must reproduce the above
--     copyright notice, this list of conditions and the following
--     disclaimer in the documentation and/or other materials
--     provided with the distribution.
--
--   * Neither the name of Mesa Electronics nor the names of its
--     contributors may be used to endorse or promote products
--     derived from this software without specific prior written
--     permission.
--
--
-- Disclaimer:
--
--     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
--     "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
--     LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
--     FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
--     COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
--     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
--     BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
--     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
--     CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
--     LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
--     ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--     POSSIBILITY OF SUCH DAMAGE.
--

use work.IDROMConst.all;

package PIN_7I96SD_Test_51 is
    constant ModuleID : ModuleIDType :=(
        (HM2DPLLTag,            x"00",    ClockLowTag,        x"01",    HM2DPLLBaseRateAddr&PadT,        HM2DPLLNumRegs,            x"00",    HM2DPLLMPBitMask),
        (WatchDogTag,            x"00",    ClockLowTag,        x"01",    WatchDogTimeAddr&PadT,            WatchDogNumRegs,        x"00",    WatchDogMPBitMask),
        (IOPortTag,                x"00",    ClockLowTag,        x"03",    PortAddr&PadT,                    IOPortNumRegs,            x"00",    IOPortMPBitMask),
        (OutMTag,                x"00",    ClockLowTag,        x"01",    OutMDataAddr&PadT,                OutMNumRegs,            x"00",    OutMMPBitMask),
        (PWMTag,                x"00",    ClockHighTag,        x"01",    PWMValAddr&PadT,                PWMNumRegs,                x"00",    PWMMPBitMask),
        (StepGenTag,            x"02",    ClockLowTag,        x"05",    StepGenRateAddr&PadT,            StepGenNumRegs,            x"00",    StepGenMPBitMask),
        (QcountTag,                x"02",    ClockLowTag,        x"06",    QcounterAddr&PadT,                QCounterNumRegs,        x"00",    QCounterMPBitMask),
        (SSerialTag,            x"00",    ClockLowTag,        x"01",    SSerialCommandAddr&PadT,        SSerialNumRegs,            x"10",    SSerialMPBitMask),
        (XFrmrOutTag,            x"00",    ClockLowTag,        x"01",    XFrmrDataAddr&PadT,                XFrmrNumRegs,            x"00",    XFrmrMPBitMask ),
        (InMTag,                x"00",    ClockLowTag,        x"01",    InMControlAddr&PadT,            InMNumRegs,                x"00",    InMMPBitMask),
        (LEDTag,                x"00",    ClockLowTag,        x"01",    LEDAddr&PadT,                    LEDNumRegs,                x"00",    LEDMPBitMask),
        (PktUARTTTag,            x"02",    ClockLowTag,        x"01",    PktUARTTDataAddr&PadT,            PktUARTTNumRegs,        x"00",    PktUARTTMPBitMask),
        (PktUARTRTag,            x"02",    ClockLowTag,        x"01",    PktUARTRDataAddr&PadT,            PktUARTRNumRegs,        x"00",    PktUARTRMPBitMask),
        (NullTag,                x"00",    NullTag,            x"00",    NullAddr&PadT,                    x"00",                    x"00",    x"00000000"),
        (NullTag,                x"00",    NullTag,            x"00",    NullAddr&PadT,                    x"00",                    x"00",    x"00000000"),
        (NullTag,                x"00",    NullTag,            x"00",    NullAddr&PadT,                    x"00",                    x"00",    x"00000000"),
        (NullTag,                x"00",    NullTag,            x"00",    NullAddr&PadT,                    x"00",                    x"00",    x"00000000"),
        (NullTag,                x"00",    NullTag,            x"00",    NullAddr&PadT,                    x"00",                    x"00",    x"00000000"),
        (NullTag,                x"00",    NullTag,            x"00",    NullAddr&PadT,                    x"00",                    x"00",    x"00000000"),
        (NullTag,                x"00",    NullTag,            x"00",    NullAddr&PadT,                    x"00",                    x"00",    x"00000000"),
        (NullTag,                x"00",    NullTag,            x"00",    NullAddr&PadT,                    x"00",                    x"00",    x"00000000"),
        (NullTag,                x"00",    NullTag,            x"00",    NullAddr&PadT,                    x"00",                    x"00",    x"00000000"),
        (NullTag,                x"00",    NullTag,            x"00",    NullAddr&PadT,                    x"00",                    x"00",    x"00000000"),
        (NullTag,                x"00",    NullTag,            x"00",    NullAddr&PadT,                    x"00",                    x"00",    x"00000000"),
        (NullTag,                x"00",    NullTag,            x"00",    NullAddr&PadT,                    x"00",                    x"00",    x"00000000"),
        (NullTag,                x"00",    NullTag,            x"00",    NullAddr&PadT,                    x"00",                    x"00",    x"00000000"),
        (NullTag,                x"00",    NullTag,            x"00",    NullAddr&PadT,                    x"00",                    x"00",    x"00000000"),
        (NullTag,                x"00",    NullTag,            x"00",    NullAddr&PadT,                    x"00",                    x"00",    x"00000000"),
        (NullTag,                x"00",    NullTag,            x"00",    NullAddr&PadT,                    x"00",                    x"00",    x"00000000"),
        (NullTag,                x"00",    NullTag,            x"00",    NullAddr&PadT,                    x"00",                    x"00",    x"00000000"),
        (NullTag,                x"00",    NullTag,            x"00",    NullAddr&PadT,                    x"00",                    x"00",    x"00000000"),
        (InMWidth0Tag,            x"00",    NullTag,            x"00",    NullAddr&PadT,                    x"00",                    x"00",    x"0000000B") -- hide this tag here until we find a better way
        );
            
    constant PinDesc : PinDescType :=(
    
--     Base func  sec unit sec func     sec pin                                   
        
                                                                            --        
        IOPortTag & x"00" & InMTag & InMData0Pin,           -- I/O 00     embedded 7I96 Simple I/O
        IOPortTag & x"00" & InMTag & InMData1Pin,           -- I/O 01       
        IOPortTag & x"00" & InMTag & InMData2Pin,           -- I/O 02   
        IOPortTag & x"00" & InMTag & InMData3Pin,           -- I/O 03        
        IOPortTag & x"00" & InMTag & InMData4Pin,           -- I/O 04    
        IOPortTag & x"00" & InMTag & InMData5Pin,            -- I/O 05        
        IOPortTag & x"00" & InMTag & InMData6Pin,           -- I/O 06   
        IOPortTag & x"00" & InMTag & InMData7Pin,           -- I/O 07       
        IOPortTag & x"00" & InMTag & InMData8Pin,            -- I/O 08   
        IOPortTag & x"00" & InMTag & InMData9Pin,           -- I/O 09   
        IOPortTag & x"00" & InMTag & InMDataAPin,           -- I/O 10   
        IOPortTag & x"00" & XfrmrOutTag & XfrmrOut0Pin,       -- I/O 11   
        IOPortTag & x"00" & XfrmrOutTag & XfrmrOut1Pin,       -- I/O 12   
        IOPortTag & x"00" & XfrmrOutTag & XfrmrOut2Pin,       -- I/O 13        
        IOPortTag & x"00" & XfrmrOutTag & XfrmrOut3Pin,       -- I/O 14       
        IOPortTag & x"00" & OutMTag & OutMData4Pin,           -- I/O 15       
        IOPortTag & x"00" & OutMTag & OutMData5Pin,           -- I/O 16       

        IOPortTag & x"00" & StepGenTag & StepGenStepPin,    -- I/O 17    embedded 7I96 Step/Dir/Enc/Serial
        IOPortTag & x"00" & StepGenTag & StepGenDirPin,        -- I/O 18    
        IOPortTag & x"01" & StepGenTag & StepGenStepPin,    -- I/O 19    
        IOPortTag & x"01" & StepGenTag & StepGenDirPin,        -- I/O 20    
        IOPortTag & x"02" & StepGenTag & StepGenStepPin,    -- I/O 21    
        IOPortTag & x"02" & StepGenTag & StepGenDirPin,        -- I/O 22    
        IOPortTag & x"03" & StepGenTag & StepGenStepPin,    -- I/O 23    
        IOPortTag & x"03" & StepGenTag & StepGenDirPin,        -- I/O 24    
        IOPortTag & x"04" & StepGenTag & StepGenStepPin,    -- I/O 25    
        IOPortTag & x"04" & StepGenTag & StepGenDirPin,        -- I/O 26    
        IOPortTag & x"00" & QCountTag & QCountQAPin,        -- I/O 27
        IOPortTag & x"00" & QCountTag & QCountQBPin,        -- I/O 28    
        IOPortTag & x"00" & QCountTag & QCountIdxPin,        -- I/O 29    
        IOPortTag & x"00" & SSerialTag & SSerialRX0Pin,        -- I/O 30    
        IOPortTag & x"00" & SSerialTag & SSerialTX0Pin,        -- I/O 31    
        IOPortTag & x"00" & SSerialTag & SSerialTXEn0Pin,    -- I/O 32    
        IOPortTag & x"00" & XfrmrOutTag & XfrmrRefPin,        -- I/O 33
        
                                        --    Expansion port
        IOPortTag & x"01" & QCountTag & QCountQAPin,                   -- I/O 34   PIN 1
        IOPortTag & x"01" & QCountTag & QCountQBPin,                   -- I/O 35   PIN 14
        IOPortTag & x"02" & QCountTag & QCountQAPin,                  -- I/O 36   PIN 2
        IOPortTag & x"02" & QCountTag & QCountQBPin,                   -- I/O 37   PIN 15
        IOPortTag & x"03" & QCountTag & QCountQAPin,                  -- I/O 38   PIN 3
        IOPortTag & x"03" & QCountTag & QCountQBPin,                   -- I/O 39   PIN 16
        IOPortTag & x"04" & QCountTag & QCountQAPin,                  -- I/O 40   PIN 4
        IOPortTag & x"04" & QCountTag & QCountQBPin,                   -- I/O 41   PIN 17
        IOPortTag & x"05" & QCountTag & QCountQAPin,                  -- I/O 42   PIN 5
        IOPortTag & x"05" & QCountTag & QCountQBPin,                   -- I/O 43   PIN 18
        IOPortTag & x"00" & PktUARTTTag & PktUTDataPin,                -- I/O 44   PIN 6
        IOPortTag & x"00" & PktUARTRTag & PktURDataPin,                -- I/O 45   PIN 19
        IOPortTag & x"00" & NullTag & x"00",                   -- I/O 46   PIN 9
        IOPortTag & x"00" & NullTag & x"00",                   -- I/O 47   PIN 10
        IOPortTag & x"00" & NullTag & x"00",                   -- I/O 48   PIN 11
        IOPortTag & x"00" & NullTag & x"00",                   -- I/O 49   PIN 12
        IOPortTag & x"00" & NullTag & x"00",                   -- I/O 50   PIN 13
        
        LIOPortTag & x"00" & PWMTag  & PWMAOutPin,             -- 7I96S analog out PWM
        LIOPortTag & x"00" & PWMTag  & PWMBDirPin,             -- dummy for now
                                                                                                        
        emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
        emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,

        emptypin,emptypin,emptypin,emptypin,emptypin,
        emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
        emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
        
        emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
        emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
        emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
        emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
        emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
        emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
        emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);

end package PIN_7I96SD_Test_51;

and the output of the mesaflash --read

Configuration Name: HOSTMOT2

General configuration information:

  BoardName : MESA7I96
  FPGA Size: 20 KGates
  FPGA Pins: 256
  Number of IO Ports: 3
  Width of one I/O port: 17
  Clock Low frequency: 100.0000 MHz
  Clock High frequency: 160.0000 MHz
  IDROM Type: 3
  Instance Stride 0: 4
  Instance Stride 1: 64
  Register Stride 0: 256
  Register Stride 1: 256

Modules in configuration:

  Module: DPLL
  There are 1 of DPLL in configuration
  Version: 0
  Registers: 7
  BaseAddress: 7000
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: WatchDog
  There are 1 of WatchDog in configuration
  Version: 0
  Registers: 3
  BaseAddress: 0C00
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: IOPort
  There are 3 of IOPort in configuration
  Version: 0
  Registers: 5
  BaseAddress: 1000
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: OutM
  There are 1 of OutM in configuration
  Version: 0
  Registers: 1
  BaseAddress: B000
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: PWM
  There are 1 of PWM in configuration
  Version: 0
  Registers: 5
  BaseAddress: 4100
  ClockFrequency: 160.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: StepGen
  There are 5 of StepGen in configuration
  Version: 2
  Registers: 10
  BaseAddress: 2000
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: QCount
  There are 6 of QCount in configuration
  Version: 2
  Registers: 5
  BaseAddress: 3000
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: SSerial
  There are 1 of SSerial in configuration
  Version: 0
  Registers: 6
  BaseAddress: 5B00
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 64 bytes

  Module: SSR
  There are 1 of SSR in configuration
  Version: 0
  Registers: 2
  BaseAddress: 7D00
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: InM
  There are 1 of InM in configuration
  Version: 0
  Registers: 5
  BaseAddress: 8500
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: LED
  There are 1 of LED in configuration
  Version: 0
  Registers: 1
  BaseAddress: 0200
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: PktUARTTX
  There are 1 of PktUARTTX in configuration
  Version: 2
  Registers: 4
  BaseAddress: 6100
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: PktUARTRX
  There are 1 of PktUARTRX in configuration
  Version: 2
  Registers: 4
  BaseAddress: 6500
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

Configuration pin-out:

IO Connections for TB3 -> 7I96_0
Pin#                  I/O   Pri. func    Sec. func        Chan     Sec. Pin func   Sec. Pin Dir

TB3-1                   0   IOPort       InM              0        Input0_EncA0    (In)
TB3-2                   1   IOPort       InM              0        Input1_EncB0    (In)
TB3-3                   2   IOPort       InM              0        Input2_EncA1    (In)
TB3-4                   3   IOPort       InM              0        Input3_EncB1    (In)
TB3-5                   4   IOPort       InM              0        Input4_EncA2    (In)
TB3-6                   5   IOPort       InM              0        Input5_EncB2    (In)
TB3-7                   6   IOPort       InM              0        Input6_EncA3    (In)
TB3-8                   7   IOPort       InM              0        Input7_EncB3    (In)
TB3-9                   8   IOPort       InM              0        Input8          (In)
TB3-10                  9   IOPort       InM              0        Input9          (In)
TB3-11                 10   IOPort       InM              0        Input10         (In)
TB3-13,14              11   IOPort       SSR              0        Out-00          (Out)
TB3-15,16              12   IOPort       SSR              0        Out-01          (Out)
TB3-17,18              13   IOPort       SSR              0        Out-02          (Out)
TB3-19,20              14   IOPort       SSR              0        Out-03          (Out)
TB3-21,22              15   IOPort       OutM             0        Output4         (Out)
TB3-23,24              16   IOPort       OutM             0        Output5         (Out)

IO Connections for TB1/TB2 -> 7I96_1
Pin#                  I/O   Pri. func    Sec. func        Chan     Sec. Pin func   Sec. Pin Dir

TB1-2,3                17   IOPort       StepGen          0        Step/Table1     (Out)
TB1-4,5                18   IOPort       StepGen          0        Dir/Table2      (Out)
TB1-8,9                19   IOPort       StepGen          1        Step/Table1     (Out)
TB1-10,11              20   IOPort       StepGen          1        Dir/Table2      (Out)
TB1-14,15              21   IOPort       StepGen          2        Step/Table1     (Out)
TB1-16,17              22   IOPort       StepGen          2        Dir/Table2      (Out)
TB1-20,21              23   IOPort       StepGen          3        Step/Table1     (Out)
TB1-22,23              24   IOPort       StepGen          3        Dir/Table2      (Out)
TB2-2,3                25   IOPort       StepGen          4        Step/Table1     (Out)
TB2-4,5                26   IOPort       StepGen          4        Dir/Table2      (Out)
TB2-7,8                27   IOPort       QCount           0        Quad-A          (In)
TB2-10,11              28   IOPort       QCount           0        Quad-B          (In)
TB2-13,14              29   IOPort       QCount           0        Quad-IDX        (In)
TB2-16,17              30   IOPort       SSerial          0        RXData0         (In)
TB2-18,19              31   IOPort       SSerial          0        TXData0         (Out)
Internal-TXEn          32   IOPort       SSerial          0        TXEn0           (Out)
Internal               33   IOPort       SSR              0        AC Ref          (Out)

IO Connections for P1 -> 7I96_2
Pin#                  I/O   Pri. func    Sec. func        Chan     Sec. Pin func   Sec. Pin Dir

P1-01/DB25-01          34   IOPort       QCount           1        Quad-A          (In)
P1-02/DB25-14          35   IOPort       QCount           1        Quad-B          (In)
P1-03/DB25-02          36   IOPort       QCount           2        Quad-A          (In)
P1-04/DB25-15          37   IOPort       QCount           2        Quad-B          (In)
P1-05/DB25-03          38   IOPort       QCount           3        Quad-A          (In)
P1-06/DB25-16          39   IOPort       QCount           3        Quad-B          (In)
P1-07/DB25-04          40   IOPort       QCount           4        Quad-A          (In)
P1-08/DB25-17          41   IOPort       QCount           4        Quad-B          (In)
P1-09/DB25-05          42   IOPort       QCount           5        Quad-A          (In)
P1-11/DB25-06          43   IOPort       QCount           5        Quad-B          (In)
P1-13/DB25-07          44   IOPort       PktUARTTX        0        TXData          (Out)
P1-15/DB25-08          45   IOPort       PktUARTRX        0        RXData          (In)
P1-17/DB25-09          46   IOPort       None           
P1-19/DB25-10          47   IOPort       None           
P1-21/DB25-11          48   IOPort       None           
P1-23/DB25-12          49   IOPort       None           
P1-25/DB25-13          50   IOPort       None           

then i hooked my osciloscope between ch1 gnd - pin7 / ch2  gnd - pin8 

and tried Andy Pugh's bash script found in HM2_PKTUART after adding the s for the 7I96s

# First setup the DDR and Alt Source regs for the 7I96
mesaflash --device 7i96 --addr 10.10.10.10 --wpo 0x1100=0x1F800
mesaflash --device 7i96 --addr 10.10.10.10 --wpo 0x1104=0x1C3FF
mesaflash --device 7i96 --addr 10.10.10.10 --wpo 0x1200=0x1F800
mesaflash --device 7i96 --addr 10.10.10.10 --wpo 0x1204=0x1C3FF
# Next set the baud rate DDS's for 9600 baud
mesaflash --device 7i96 --addr 10.10.10.10 --wpo 0x6300=0x65
mesaflash --device 7i96 --addr 10.10.10.10 --wpo 0x6700=0x65
# setup the TX and RX mode registers
mesaflash --device 7i96 --addr 10.10.10.10 --wpo 0x6400=0x00062840
mesaflash --device 7i96 --addr 10.10.10.10 --wpo 0x6800=0x3FC61408
# Reset the TX and RX UARTS
mesaflash --device 7i96 --addr 10.10.10.10 --wpo 0x6400=0x80010000
mesaflash --device 7i96 --addr 10.10.10.10 --wpo 0x6800=0x80010000
# load 7 bytes of data into the TX UART
mesaflash --device 7i96 --addr 10.10.10.10 --wpo 0x6100=0x54535251
mesaflash --device 7i96 --addr 10.10.10.10 --wpo 0x6100=0x58575655
mesaflash --device 7i96 --addr 10.10.10.10 --wpo 0x6100=0x64636261
mesaflash --device 7i96 --addr 10.10.10.10 --wpo 0x6100=0x68676665
# Command the TX UART to send 8 bytes twice
mesaflash --device 7i96 --addr 10.10.10.10 --wpo 0x6200=0x08
mesaflash --device 7i96 --addr 10.10.10.10 --wpo 0x6200=0x08
sleep .1
# display the RX mode reg, RX count, and the data
mesaflash --device 7i96 --addr 10.10.10.10 --rpo 0x6800
mesaflash --device 7i96 --addr 10.10.10.10 --rpo 0x6600
mesaflash --device 7i96 --addr 10.10.10.10 --rpo 0x6500
mesaflash --device 7i96 --addr 10.10.10.10 --rpo 0x6500
mesaflash --device 7i96 --addr 10.10.10.10 --rpo 0x6800
mesaflash --device 7i96 --addr 10.10.10.10 --rpo 0x6600
mesaflash --device 7i96 --addr 10.10.10.10 --rpo 0x6500
mesaflash --device 7i96 --addr 10.10.10.10 --rpo 0x6500

Nothing -- constant 5V on both channels

pls advice

 

For a DM542, I would wire:

DRIVE      7I96S

STEP+      +5V
DIR+        +5V
STEP-        STEP-
DIR-          DIR-
ENA+       NC
ENA-        NC


 

Are there any red lights illuminated on the 7C81?

Also it's never a good idea to do a flash write command unless
communication with the card is known to work and be reliable
(test with a read command)

Well, I thought about that option for some time.  My problem is, I don't have the budget (and can't get financing) for a cnc router at this time.  I don't have much extra time either,  but I have even less extra money. Lol.  

My thoughts on using this machine are as follows.  
1. I already have it.  My dad bought this on a whim 6ish years ago thinking i could do something with it, and brought it to my shop. ( I wasn't in business then, just working as a hobby)
2. It's stout.  It weighs right at 3000 pounds, so very sturdy.
3. it has x and y axis already, and they are working.
4. It already has a vacuum table and pump.
5.  The only work I have to do is modify the gantry, bolt on a z axis and spindle, and get the programming ready.  (Fully auto Atc functions, 4th axis lathe, etc will be added way down the line)

yes it would be easier and faster to just purchase a machine, but like I said I dont have the budget for that.  My budget for this machine is about $3000.  I dont think I could get a machine this large, stable,  already with a vac table for that.

Hi,I am owner of a fngj 40 milling machine, which i want to convert to linuxcnc.
The x and y axis are already converted to ballscrews.
The machine mounts a broken acu rite 2 axis cnc control
At first look the glass scales seem to be incremental with index.
The servos seem to be brushed analog servos.
Thats what i know at the moment.
Now to my questions
- the Z axis mounts a acme thread with a revolving nut, which makes a conversion to basscrew a bit complicated, so if anyone has an idea or already converted such a machine, i would apreciate some help.
- I would like to realize the control with a j3455 and mesa cards. I would like to reuse the analog servos, encoders and maybe add 2 step dir axis. And of course i would need 5/5 or so digital i/o. What would be a good choice?
- does anyone know if those acu rite millpwr servo drives can be reused with lcnc/mesa hardware?
I an pretty shure there will be some questions over the time, so thank you in advance.