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What are the spindle P terms (in the ini file)

In general for spindle setup, I would get open loop operation
running correctly first before trying to close the loop.

Basically if you have a spindle PID loop, this means setting
FF0 to 1  and all other PID gains to 0
 

Your table is missing the channel data, not sure why, but this is what I get:

IO Connections for TB1/TB2 -> 7I96_1
Pin#                  I/O   Pri. func    Sec. func        Chan     Sec. Pin func   Sec. Pin Dir

TB1-2,3                17   IOPort       StepGen          0        Step/Table1     (Out)
TB1-4,5                18   IOPort       StepGen          0        Dir/Table2        (Out)
TB1-8,9                19   IOPort       StepGen          1        Step/Table1      (Out)
TB1-10,11            20   IOPort       StepGen          1        Dir/Table2        (Out)
TB1-14,15            21   IOPort       StepGen          2        Step/Table1      (Out)
TB1-16,17            22   IOPort       StepGen          2        Dir/Table2        (Out)
TB1-20,21            23   IOPort       StepGen          3        Step/Table1      (Out)
TB1-22,23            24   IOPort       StepGen          3        Dir/Table2        (Out)
TB2-2,3                25   IOPort       StepGen          4        Step/Table1      (Out)
TB2-4,5                26   IOPort       StepGen          4        Dir/Table2        (Out)
TB2-7,8                27   IOPort       QCount            0        Quad-A            (In)
TB2-10,11            28   IOPort       QCount            0        Quad-B            (In)
TB2-13,14            29   IOPort       QCount            0        Quad-IDX         (In)
TB2-16,17            30   IOPort       SSerial             0        RXData0          (In)
TB2-18,19            31   IOPort       SSerial             0        TXData0          (Out)
Internal-TXEn       32   IOPort       SSerial             0        TXEn0             (Out)
Internal                33   IOPort       SSR                  0        AC Ref            (Out)

Default firmware on a 7I96S is 7i96s_d.bin

 

Currently they time the RX and TX data transfer overhead:

EtherRecv2Mem
        sta     SetTP0
        lda     recvfcount      ; already doing a multi frame recv,
        jmpnz   recvframe       ; so skip the prelims   

.......

recvdone
        lwi     1
        addto   recvpktcount
        lwi     MinusSix                ;adjust for CRC and 2 byte offset
        addto   recvpktsize
        sta     ClrTP0
        ret

EtherSendFromMem
        sta     SetTP1
        lda     sendpktsize             
        add     threeloc

.......

        lwi     1
        addto   sendpktcount  
        sta     ClrTP1
        ret     




 

Although, I don't understand why the pin func for the Stepgens are all "Step/Table1" and "Dir/Table2". I would have expected an index between 1 and 5 (or 0 and 4).