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There are 3 clocks because there are 3 BISS channels in that configuration

in addition you mast set the DPLL timer so that the BISS read completes before the nominal read time
something like:

setp hm2_5i25.0.dpll.01.timer-us -200

The 7I74 only outputs 5V signals so no 10V signal is possible other than
perhaps overshoot on an unterminated line.

The outputs swing from ground to +5V, so If you measure between
outputs, you could read +5V or -5V depending on the output state.

 

I think he is right, I tend for option 1 as well, actually already have it work pretty well in my testing.
Option 2 which is what the big boys use, Siemens Fanuc etc. as far as we understand, requires a complete TP rewrite

Hi,

ist ja nicht mein Thread aber vielleicht als Vorschlag, weil wir ja doch einiges thematisiert haben:

Möglichkeiten höherer Logikspannungen (>5V) für Endstufen (7i96(s) und Parallelport)

Yes, you can "addf" the and2 functions separately. This isn't true for all HAL components, some have a single read and/or write thread for all instances.

But for and2 you could have:

It is possible to retrospectively add functions in a position other than the end, if you really need to:



This seems to be less well documented than one might wish. Possibly it doesn't work properly. I think that positive numbers are position from the start and negative position from the end.

github.com/LinuxCNC/linuxcnc/blob/master...cmd_commands.cc#L318

Unless the supplier has documentation we can only guess at how the board is set up and how it works.

You could try to use the manual for the _real_ 7i92 from here:
www.mesanet.com/pdf/parallel/7i92tman.pdf

But if there are differences, then you may be on your own.

The ultimate goal is to have both Option 1 and Option 2. Jerk limited velocity planning AND G2-continuous transition curves.

Option 2 is where jerk limiting goes to die in linuxcnc.

Not sure what makes you say that as one does not exclude the other they actually complement each other.

20k latency seems fairly decent. With a base period of 50,000 that should never over-run.

Jerk limiting should in no way affect the path. Ever.

g64 smoothing should ideally be decoupled from jerk limiting - it functionally has a built in jerk limiting as it is.

Acceptable choices are:

1: NOT use jerk limiting on smoothed line to line transitions - only jerk limit the start and end and any breaks in smoothing (acute angles etc), and then all exact stop moves. This will make motion smooth in almost all critical cases.

2: Create a new constant velocity planner with jerk limited smoothing strategies.

Option 2 is where jerk limiting goes to die in linuxcnc. I would focus on option one and making it 100% fully stable - you seem to have a good proof of concept started, but still have a ways to go. I would not get side tracked by trying to reinvent what already works quite well.

By using the asda2e you can use the 14 dinputs and 5 doutputs of the drive and spare the extra digital io modules.

It worked, thank you.

My personal opinion is to default to #1. But as G64P tolerance increases allow more path tolerance so that velocity deviation can decrees.

i found it i got my clock.
i needed this two line:
setp hm2_5i25.0.biss.00.timer-number 1
setp hm2_5i25.0.biss.00.frequency-khz 8000.
i just want to know if it is ok to have 10 volt of amplitude between -5 clk- and +5 clk+ with spike to -10 +10 v? seem a bit much for a clock, WIll test other cable i may have made a mistake here.

Huh, thought I'd posted again last thing last night but it doesn't seem to have taken.

We tried the 7i80HD-25 card with the -25 version of the firmware you sent, and with this in the system, the encoder ports are being read as expected (apart from how Yaskawa servopack C-channel vs Z-channel isn't as expected at all).

I would be grateful if you could send the firmware for that card including: 6x analogue servo, 6x encoder, 2x pktuart and 2x sserial modules, for 7i80HD-25, 7i48, 7i52 combination.

Thanks in advance!

Probably more like this where a bitmap exists. Note that in places its padded with unused bits 

i am not making any progress so let take a step back.
i use a bit file PIN_7I76_7I74BISS3D_34 With the biss signal assigned to a 7i74 plugged on the port P2 with the pin configuration :
        IOPortTag & x"00" & BISSTag  & BISSDataPin,             -- I/O 17    PIN 1
        IOPortTag & x"01" & BISSTag  & BISSDataPin,             -- I/O 18    PIN 14
        IOPortTag & x"02" & BISSTag  & BISSDataPin,             -- I/O 19    PIN 2
        IOPortTag & x"00" & NullTag & x"00",                    -- I/O 20    PIN 15
        IOPortTag & x"00" & BISSTag  & BISSClkPin,            -- I/O 21    PIN 3
        IOPortTag & x"01" & BISSTag  & BISSClkPin,            -- I/O 22    PIN 16
        IOPortTag & x"02" & BISSTag  & BISSClkPin,            -- I/O 23    PIN 4
I dont understand yet why we have 3 pin for data and 3 for clock but its fine.

the objective now is to get the system to produce at least a clock. with the cnc project running i tried to locate where the clock where available but nothing. I tested each port rj45 on my 7i74 and even the pin from the cable between my two card and nothing relevant. i got power (5v) some signal but no clock. do i need a command in hal/init /bit/god? to indicate that the signal should be active?