Index homing Mesa 7i96s

Yes, I tried but again the bit file doesn't compile.
For testing, I removed 2 step generators and there is no change. I am attaching the log file from ISE Design Suite 14.7

I apologize for taking up so much of your time.Thank you very much for the help !

 


PS. I did an experiment. I removed the changes for the shared index. I left only the new changes on the multiplexer inputs. Again the bit file is not created.

New update .I can manually create a bit file . But it comes with several warning messages and one error

WARNING:Bitgen:284 - Setting next_config_register_write to Disable will cause
   the next_config_addr, next_config_new_mode, and next_config_boot_mode options
   to be ignored and their respective register writes to be excluded from the
   bitstream.
INFO:Bitgen:341 - This design is using one or more 9K Block RAMs (RAMB8BWER). 
   9K Block RAM initialization data, both user defined and default, requires a
   special bit stream format.  For more information, please reference Xilinx
   Answer Record 39999.
WARNING:PhysDesignRules:367 - The signal
   <ahostmot2/makesserialmod.makesserials[0].asserial/processor/StackRam/Mram_RA
   M1_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <ahostmot2/makesserialmod.makesserials[0].asserial/processor/StackRam/Mram_RA
   M2_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the
   design.
INFO:PhysDesignRules:1861 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM comp ClockMult1, consult the
   device Data Sheet.
INFO:PhysDesignRules:1861 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM comp ClockMult2, consult the
   device Data Sheet.
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
   (RAMB8BWER).  9K Block RAM initialization data, both user defined and
   default, may be incorrect and should not be used.  For more information,
   please reference Xilinx Answer Record 39999.

FATAL_ERROR:Bitstream:stanbsbitfile.c:3408:1.57 - Incorrect number of bits in
   bitstream (18) for FDRI write.   For technical support on this issue, please
   visit www.xilinx.com/support .


 

PS. I loaded the file into the board it seems to work.  The multiplexer pins are visible in the HAL 
If the board works, the error is not important?


 

Yeah the log file was OK (though it looked like you did not select the option to make the bit file)

It looks like the bit file error is related to running ISE on Windows 10 or 11 but not selecting compatibility mode
(I always use Linux now so I've never seen that error)

Thank you very much! Yes, the OS is Windows 10.

Hi

I also could use some index inputs for my Emco lathe. Is it possible to make a firmware for 7i96S with 2 index inputs in isolated I/O?

Its possible, but would need slow index inputs (at least 300 usec or so in duration)
what does you index signal come from?