Absolute Encoder Questions / SSI via 5i25

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21 Oct 2012 08:36 - 21 Oct 2012 08:38 #25532 by juwi
from the "regmap.txt"

"SSI Data Register, right justifed. Writes to this location will start a
read cycle for the specific SSI interface addressed"

I dont understand this? If these are the read data registers, why shall I write to them? Or does it mean "clear after read for new data"?

My Drives are Stoeber Posidyn, I can set them to grey or binary encoding. Imho it would be the simplest just to make the driver put out a grey-pin and a binary-pin. One of them is usable for you in any case...

@PCW: How can I enable the SSI in my 5i25 / 7i77 card combo? I only could find BISS in a source file... No SSI?

Thanks for your help!

julian
Last edit: 21 Oct 2012 08:38 by juwi.

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21 Oct 2012 10:35 #25534 by andypugh
juwi wrote:

"SSI Data Register, right justifed. Writes to this location will start a
read cycle for the specific SSI interface addressed"
I dont understand this? If these are the read data registers, why shall I write to them? Or does it mean "clear after read for new data"?


Its a feature of the FPGA. (and one that confused me at first).
Any register address can be considered as two separate registers, one for reading and one for writing.
Many of the registers are write-only, you can write data to them, but reads always return 0xFFFFFFFF.
Others may be read-only, you can read valid data from them but writes are quietly ignored.
Some are read/write, but there should be no expectation of any correspondence between the data written and what is read back. Consider it as two separate registers with the same hex address.

Writes to FPGA registers can trigger actions. (I am not sure if reads do too). In this case it sounds like any write to those registers (value unimportant) will trigger a read cycle.

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21 Oct 2012 14:54 #25547 by PCW
Thats exactly right. SSI is a synchronous serial interface very much like SPI except it has no CS (Chip Select) signal and its unidirectional.

Writing the data register will start a transfer of the selected channel. then the host CPU must wait for the transfer to complete before reading the data register.

For more than one axis, it's probably better to start all read cycles at once
using the global start register

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21 Oct 2012 15:00 #25548 by PCW

@PCW: How can I enable the SSI in my 5i25 / 7i77 card combo? I only could find BISS in a source file... No SSI?


This requires
1 Creating a pinout file for the SSI interface that matches the desired daugherecard pinout
2 Recompiling the VHDL source
3.Writing the 5i25s EEPROM with new bitfile
(number 3 is a bit risky with an untested bitfile if you dont have a JTAG programming cable)

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21 Oct 2012 15:47 #25553 by juwi
PCW wrote:

@PCW: How can I enable the SSI in my 5i25 / 7i77 card combo? I only could find BISS in a source file... No SSI?


This requires
1 Creating a pinout file for the SSI interface that matches the desired daugherecard pinout
2 Recompiling the VHDL source
3.Writing the 5i25s EEPROM with new bitfile
(number 3 is a bit risky with an untested bitfile if you dont have a JTAG programming cable)


I have a avr dragon. Is this a jtag programmer I can use?

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21 Oct 2012 17:22 #25556 by PCW
I doubt it unless it is compatible with some Xilinx cable or you have
Xilinx compatible download software for it

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21 Oct 2012 19:16 - 21 Oct 2012 19:18 #25563 by Dave911
juwi,

I need to alter the Hostmot2 driver to add an SSI interface to a Balluff linear position sensor and would like to add the code into the driver so it can work with rotary encoders as well.

I have a Balluff Linear encoder and cable being shipped to me. I already have Mesa hardware - a 7i43 200K unit and a 7i47 RS22 interface card.

Peter (PCW) has compiled a bit file for the 7i43 which includes the SSI interface.

The Balluff SSI interface is very simple. There is no rotary - rotation count, rotation increment - components for the interface. It simply maps the linear encoder length to the the full range of bits - either 24 or 25 bits and it does it in a binary format.

I don't have a rotary encoder at the moment so I would like to work on this with you on this if you are up for it.

I'm not sure if the 5i25/7i77 card is a suitable hardware setup to use with SSI or not.

I also have a 5i20 card that I can use for testing - if that matters. I'd like to also get the SSI interface verified with the 5i20 card as well, after the 7i43 implementation is verified.

I have two customers who would like to take advantage of this interface, so I am motivated.

I have the SSI version of this sensor on its way.
www.balluff.com/balluff/MUS/en/products/...al-Mount-Profile.jsp

My direct email address is Dave @ Cole Controls . com (remove spaces)

All comments, advice etc are welcome. :)

Regards,

Dave
Last edit: 21 Oct 2012 19:18 by Dave911. Reason: added name

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21 Oct 2012 20:06 #25565 by juwi
PCW wrote:

I doubt it unless it is compatible with some Xilinx cable or you have
Xilinx compatible download software for it


OK...
So, I am missing the ability to compile and test vhdl.

@PCW:
Would you be so kind and compile me a bios for the 5i25 / 7i77 combo using the serial port on the 7i77 as SSI interface?

As far as I read the driver code this shall be doable.

@PCW:
Would it be possible to use the raw pins on the second port of the 5i25 as SSI?

-> 17 IOs per Connector - 4 per SSI => 4x SSI

I am not afraid of the driver code, thats stuff I work with regularly. But I never did anithing with FPGAs... And shooting down my 5i25 would frustrate me.

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21 Oct 2012 20:11 #25566 by juwi
Dave911 wrote:

juwi,

Peter (PCW) has compiled a bit file for the 7i43 which includes the SSI interface.

Perhaps I could get a file from him too (looking sweet with large eyes ;) )

The Balluff SSI interface is very simple. There is no rotary - rotation count, rotation increment - components for the interface. It simply maps the linear encoder length to the the full range of bits - either 24 or 25 bits and it does it in a binary format.

Mine is the same, only the content is different

25Bit, last always zero, first 12 are degree of rotation, next 12 are turns.

Binary or grey coded.

best regards
Julian

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21 Oct 2012 21:21 #25572 by PCW
I can compile a 7I77 bit file some time next week

The raw interface is probably OK for the XMIT side but questionable
on receive because of common mode range. I would always want a real RS-422 driver/receiver there just for ruggedness however

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