Absolute Encoder Questions / SSI via 5i25
27 Aug 2013 17:13 #38142
by andypugh
Replied by andypugh on topic Absolute Encoder Questions / SSI via 5i25
What does signed gray-code look like?
ie, how do gray-code multi-turn encoders indicate a negative count?
ie, how do gray-code multi-turn encoders indicate a negative count?
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27 Aug 2013 18:09 #38146
by andypugh
Is this something that would be controlled from the driver level, or something built into the Hostmot2 module?
Replied by andypugh on topic Absolute Encoder Questions / SSI via 5i25
This is essentially what the DPLL timer system does except that it requires no base thread
Is this something that would be controlled from the driver level, or something built into the Hostmot2 module?
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27 Aug 2013 20:42 #38151
by PCW
Replied by PCW on topic Absolute Encoder Questions / SSI via 5i25
I dont think encoders (or hardware encoder counters)
commonly use signed numbers
The count is pretty much always straight binary which may be interpreted as
twos complement signed number if desired. So for gray code its gray --> binary -->
cast as twos comp --> cast as scaled float
Once setup, the DPLL just needs to be read at the reference time point, probably the beginning of the
servo thread. The read acquires the current DPLL count and has the side effect of adjusting
the rate (I) and phase (P) of the DPLL depending on the phase error.
The driver does need to set the DPLL base frequency, and wait till lock is established before using the timer outputs
I have not decided how much of the DPLL setup info needs to be exposed or whether "one size fits all" for linuxcnc
applications (setup info includes P,I gains, lock range, force lock etc)
commonly use signed numbers
The count is pretty much always straight binary which may be interpreted as
twos complement signed number if desired. So for gray code its gray --> binary -->
cast as twos comp --> cast as scaled float
Once setup, the DPLL just needs to be read at the reference time point, probably the beginning of the
servo thread. The read acquires the current DPLL count and has the side effect of adjusting
the rate (I) and phase (P) of the DPLL depending on the phase error.
The driver does need to set the DPLL base frequency, and wait till lock is established before using the timer outputs
I have not decided how much of the DPLL setup info needs to be exposed or whether "one size fits all" for linuxcnc
applications (setup info includes P,I gains, lock range, force lock etc)
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27 Aug 2013 20:58 #38152
by andypugh
So, what is the output pattern from a mutli-turn gray-code encoder that is rotated half a turn backwards?
(A problem reported with the current SSI driver code is that it only counts upwards, and I am trying to figure out if this is due to the gray-code conversion)
Replied by andypugh on topic Absolute Encoder Questions / SSI via 5i25
I dont think encoders (or hardware encoder counters)
commonly use signed numbers
The count is pretty much always straight binary which may be interpreted as
twos complement signed number if desired.
So, what is the output pattern from a mutli-turn gray-code encoder that is rotated half a turn backwards?
(A problem reported with the current SSI driver code is that it only counts upwards, and I am trying to figure out if this is due to the gray-code conversion)
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27 Aug 2013 22:47 #38157
by PCW
Replied by PCW on topic Absolute Encoder Questions / SSI via 5i25
What missing is likely sign extension.
so extract field (some SSI encoders have status bits that need to be skipped)
--> Gray --> binary --> sign extend to 32 bits --> cast to signed 32 bits --> cast to real and scale
so extract field (some SSI encoders have status bits that need to be skipped)
--> Gray --> binary --> sign extend to 32 bits --> cast to signed 32 bits --> cast to real and scale
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28 Aug 2013 00:32 #38161
by andypugh
How do we decide if the encoder is sending signed or unsigned?
It would be relatively easy to sign-extend, as long as the Hostmot2 code isn't already doing so when it populates the 32-bit registers.
This probably isn't the problem, as I think you get the issue reported by turning the encoder from a positive value to a smaller positive value.
Replied by andypugh on topic Absolute Encoder Questions / SSI via 5i25
What missing is likely sign extension.
so extract field (some SSI encoders have status bits that need to be skipped)
--> Gray --> binary --> sign extend to 32 bits --> cast to signed 32 bits --> cast to real and scale
How do we decide if the encoder is sending signed or unsigned?
It would be relatively easy to sign-extend, as long as the Hostmot2 code isn't already doing so when it populates the 32-bit registers.
This probably isn't the problem, as I think you get the issue reported by turning the encoder from a positive value to a smaller positive value.
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28 Aug 2013 01:14 #38166
by PCW
Replied by PCW on topic Absolute Encoder Questions / SSI via 5i25
AFAIK there are no signed absolute encoders as there is no benefit,
but you must sign extend the (arbitrary word size) data to the
the data size of the signed number or you will only get positive numbers
(assuming the unfilled MSBs were 0)
but you must sign extend the (arbitrary word size) data to the
the data size of the signed number or you will only get positive numbers
(assuming the unfilled MSBs were 0)
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28 Aug 2013 15:26 #38182
by andypugh
If the numbers from the encoders are always positive then I am not seeing what sign-extension will do.
What the code actually does (and it works for the Resolvers) is consider the last and current register value read from the FPGA and to add the delta to the 64-bit accumulator.
s64_accum += (new - old)
It then, separately, checks for the delta being more than half a cycle and explicity adds or subtracts a wrap (and emulates an index)
If new and old are unsigned numbers then it is probably better to us an alternative form:
s64_accum += new ; s64_accum -= old;
Which I think will work more reliably for u32 values.
Replied by andypugh on topic Absolute Encoder Questions / SSI via 5i25
AFAIK there are no signed absolute encoders as there is no benefit,
but you must sign extend the (arbitrary word size) data to the
the data size of the signed number or you will only get positive numbers
(assuming the unfilled MSBs were 0)
If the numbers from the encoders are always positive then I am not seeing what sign-extension will do.
What the code actually does (and it works for the Resolvers) is consider the last and current register value read from the FPGA and to add the delta to the 64-bit accumulator.
s64_accum += (new - old)
It then, separately, checks for the delta being more than half a cycle and explicity adds or subtracts a wrap (and emulates an index)
If new and old are unsigned numbers then it is probably better to us an alternative form:
s64_accum += new ; s64_accum -= old;
Which I think will work more reliably for u32 values.
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28 Aug 2013 20:35 #38190
by PCW
Its not needed if you always use count deltas but this makes me a little uneasy with a
multiturn or linear absolute encoder, where a straight gray --> binary --> sign extend --> cast to S32
works
Replied by PCW on topic Absolute Encoder Questions / SSI via 5i25
If the numbers from the encoders are always positive then I am not seeing what sign-extension will do.
Its not needed if you always use count deltas but this makes me a little uneasy with a
multiturn or linear absolute encoder, where a straight gray --> binary --> sign extend --> cast to S32
works
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28 Aug 2013 20:51 #38191
by andypugh
It should mean that we can count to 64-bits on any encoder. The multi-turn ones will (probably) never trigger the wrap code, but if they do then LinuxCNC won't even know.
Replied by andypugh on topic Absolute Encoder Questions / SSI via 5i25
Its not needed if you always use count deltas but this makes me a little uneasy with a
multiturn or linear absolute encoder, where a straight gray --> binary --> sign extend --> cast to S32
works
It should mean that we can count to 64-bits on any encoder. The multi-turn ones will (probably) never trigger the wrap code, but if they do then LinuxCNC won't even know.
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