Absolute Encoder Questions / SSI via 5i25

No smart serial commands will work (SSI stands for Synchonous Serial Interface) It is a very simple way to communicate with absolute encoders.

The hardware works like this: on command the host sends out a burst of clock pulses and the encoder responds with a serial data stream of position data
(often in gray code)

raw-read/raw-write hm2 interface is very low level, you can just read/write physical registers.

This is enough to verify SSI interface operation (in conjunction with the register information for the SSI interface) but not a lot more

Earlier it this thread I detailed what I thought was required of a flexible SSI interface (bit field extraction, gray code conversion) etc

PCW wrote:

The clock input/data output are normally just 5V RS-422 but you should check the data sheet. The encoder I have is the same :10-30V power RS-422 input and output levels. Mine happens to be 12 bits of counts per turn and 12 bits of turn counts, both in gray scale

I have a linear encoder, but almost the same specs:
The type of transmission protocol is "right aligned" with a length of 25 bit. The transmission starts with MSB (most significant bit) and ends with LSB (less significant bit). Unused bits are set to 0 (zero). The output code of the sensor is GRAY.
Besides clock and data pins, it has inputs for zeroing and reversing. Though I could live without those.

That is the driver has to provide clock signal, read 25 bit reply and convert it from Gray code.

PCW wrote:

raw-read/raw-write hm2 interface is very low level, you can just read/write physical registers.

This is enough to verify SSI interface operation (in conjunction with the register information for the SSI interface) but not a lot more

Can you give me the commands that you use to communicate with your encoder? I'll have it on 7i76 (or 7i77 if nesessary) port.

Do I need the firmware that you made earlier in this thread?

Really it isn't... but I start figuring it out. What I was most scared of is low-level SSI communication (sending a clock sequence and reading the reply), but I see that hm2 does that with Simple SSI interface.

Say I connected the encoder to 7i76. Now it's on SSI data register 0?

The following is my guess:

I need to set the number of encoder bits (25) and probably set program start mask to SSIBitCountRegister 0, that is

setp hm2_5i25.0.raw.write_address 0x6900
setp hm2_5i25.0.raw.write_data 89 (25 to 0...5 bits and 1 to bit 6 for Program Start Mask)
setp hm2_5i25.0.raw.write_strobe 1

SSI Bit Rate register should be set. CLockLow is 50MHz for 5i25.
The encoder has a frequency of data transmission from 100 kHz to 1 MHz, it must be the Shift frequency.
Then for 500kHz I need to set SSI Bit Rate register to 65536*500000/50000000 = 655

setp hm2_5i25.0.raw.write_address 0x6A00
setp hm2_5i25.0.raw.write_data 655
setp hm2_5i25.0.raw.write_strobe 1

Then I have 2 ways to start the reading cycle: either write (anything?) to SSI Global Start register (as the Program Start Mask is set to 1) or write (anything?) to SSI data register 0
Say I choose the second way (which is not logical as I just set the program start mask bit):

setp hm2_5i25.0.raw.write_address 0x6800
setp hm2_5i25.0.raw.write_data 1
setp hm2_5i25.0.raw.write_strobe 1

To see the returned value:

setp hm2_5i25.0.raw.read_address 0x6800
show pin hm2_5i25.0.raw.read_data

Please check if that's correct

I'll check that on Monday... occasionally left the encoders at my office.

If that proves to work, is it possible to make a thread to start the reading cycle, then connect the hm2_5i25.0.raw.read_data to some "grey-to-abs" component (probably not so hard to make) and have the encoder working?

One detail left out is is that the DDR and AltSrc register bits for the clock output pin would need to be set to one (since the driver does not know about the SSI tags)
Also if you use the latest firmware source, the SSI registers have changed:
The max data length has been extended to 64 bits to allow double-reading
for data verification, so the control reg has moved to 0x6A00

included here:



is a up-to-date regmap file and example program source
for reading the encoder

PCW wrote:

One detail left out is is that the DDR and AltSrc register bits for the clock output pin would need to be set to one (since the driver does not know about the SSI tags)

I looked through 7i76 manual, there are SS0TX (IO10) and SS1TX (IO12) pins, which is used for RS-422 interface on TB3?

I'm trying the above described, but nothing for now. Even no clock sequence on the scope.

When setting 0x6A00 it remains the same 0xFFFFFFFF (while 0x1100 changes when I write to it). What should be the default value for 0x6A00?

I purchased 7i76-5i25 PnG kit on June 2013, is it possible that the firmware has no SSI? The latest 7i76x2.bit is dated 2013-02-22, so I guess my card should have it?