LinuxCNC-RIO - RealtimeIO for LinuxCNC based on FPGA (ICE40 / ECP5)

#:/usr/src/riocore$ PYTHONPATH=. python3 bin/rio-generator riocore/configs/Spartan6/config-test.json 
loading: riocore/configs/Spartan6/config-test.json
loading board setup: Spartan6
writing gateware to: Output/Spartan6/Gateware
!!! gateware changed: needs to flash |||
loading toolchain ise
writing linuxcnc files to: Output/Spartan6/LinuxCNC

#:/usr/src/riocore/Output/Spartan6/Gateware$ clear ; make clean all




rm -rf rio.ngc rio.ngd rio.ncd parout.ncd rio.bit
cat debouncer.v toggle.v pwmmod.v rio.v > rio-modules.v
echo 'run -ifn rio-modules.v -ifmt Verilog -ofn rio.ngc -top rio -p xc6slx9-3tqg144 -opt_mode Speed -opt_level 1' | xst
Release 14.7 - xst P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
--> 

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "rio-modules.v"
Input Format                       : Verilog

---- Target Parameters
Output File Name                   : "rio.ngc"
Target Device                      : xc6slx9-3tqg144

---- Source Options
Top Module Name                    : rio

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1

=========================================================================


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Analyzing Verilog file "rio-modules.v" into library work
Parsing module <debouncer>.
Parsing module <toggle>.
Parsing module <pwmmod>.
Parsing module <rio>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating module <rio>.
WARNING:HDLCompiler:872 - "rio-modules.v" Line 94: Using initial value of ESTOP since it is never assigned
WARNING:HDLCompiler:1127 - "rio-modules.v" Line 98: Assignment to ERROR ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "rio-modules.v" Line 121: Assignment to tx_data ignored, since the identifier is never used
WARNING:HDLCompiler:634 - "rio-modules.v" Line 103: Net <rx_data[7]> does not have a driver.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <rio>.
    Related source file is "/usr/src/riocore/Output/Spartan6/Gateware/rio-modules.v".
        BUFFER_SIZE = 16'b0000000000101000
WARNING:Xst:647 - Input <sysclk_in> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <rx_data<7>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
    no macro.
Unit <rio> synthesized.

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <rio> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 0) on block rio, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Found no macro
=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : rio.ngc

Primitive and Black Box Usage:
------------------------------
# BELS                             : 1
#      GND                         : 1
# IO Buffers                       : 1
#      OBUF                        : 1

Device utilization summary:
---------------------------

Selected Device : 6slx9tqg144-3 


Slice Logic Utilization: 

Slice Logic Distribution: 
 Number of LUT Flip Flop pairs used:      0
   Number with an unused Flip Flop:       0  out of      0         
   Number with an unused LUT:             0  out of      0         
   Number of fully used LUT-FF pairs:     0  out of      0         
   Number of unique control sets:         0

IO Utilization: 
 Number of IOs:                           2
 Number of bonded IOBs:                   1  out of    102     0%  

Specific Feature Utilization:

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -3

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: No path found

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================

Cross Clock Domains Report:
--------------------------

=========================================================================


Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 3.96 secs
 
--> 


Total memory usage is 361140 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    6 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ngdbuild -p xc6slx9-3tqg144 -uc pins.ucf rio.ngc
Release 14.7 - ngdbuild P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

Command Line: /data/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -p
xc6slx9-3tqg144 -uc pins.ucf rio.ngc

Reading NGO file "/usr/src/riocore/Output/Spartan6/Gateware/rio.ngc" ...
Gathering constraint information from source properties...
Done.

Annotating constraints to design from ucf file "pins.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
Done...

Checking expanded design ...

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "rio.ngd" ...
Total REAL time to NGDBUILD completion:  2 sec
Total CPU time to NGDBUILD completion:   2 sec

Writing NGDBUILD log file "rio.bld"...

NGDBUILD done.
map -detail -pr b rio.ngd
Release 14.7 - Map P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
Using target part "6slx9tqg144-3".
Mapping design into LUTs...
Writing file rio.ngm...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 3 secs 
Total CPU  time at the beginning of Placer: 3 secs 

Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis (Checksum:1f2fb3a9) REAL time: 3 secs 

Phase 2.7  Design Feasibility Check
Phase 2.7  Design Feasibility Check (Checksum:1f2fb3a9) REAL time: 3 secs 

Phase 3.31  Local Placement Optimization
Phase 3.31  Local Placement Optimization (Checksum:1f2fb3a9) REAL time: 3 secs 

Phase 4.2  Initial Placement for Architecture Specific Features
Phase 4.2  Initial Placement for Architecture Specific Features
(Checksum:1f2fb3a9) REAL time: 4 secs 

Phase 5.36  Local Placement Optimization
Phase 5.36  Local Placement Optimization (Checksum:1f2fb3a9) REAL time: 4 secs 

Phase 6.30  Global Clock Region Assignment
Phase 6.30  Global Clock Region Assignment (Checksum:1f2fb3a9) REAL time: 4 secs 

Phase 7.3  Local Placement Optimization
Phase 7.3  Local Placement Optimization (Checksum:1f2fb3a9) REAL time: 4 secs 

Phase 8.5  Local Placement Optimization
Phase 8.5  Local Placement Optimization (Checksum:1f2fb3a9) REAL time: 4 secs 

Phase 9.8  Global Placement
Phase 9.8  Global Placement (Checksum:1f2fb3a9) REAL time: 4 secs 

Phase 10.5  Local Placement Optimization
Phase 10.5  Local Placement Optimization (Checksum:1f2fb3a9) REAL time: 4 secs 

Phase 11.18  Placement Optimization
Phase 11.18  Placement Optimization (Checksum:1f2fb3a9) REAL time: 4 secs 

Phase 12.5  Local Placement Optimization
Phase 12.5  Local Placement Optimization (Checksum:1f2fb3a9) REAL time: 4 secs 

Phase 13.34  Placement Validation
Phase 13.34  Placement Validation (Checksum:1f2fb3a9) REAL time: 4 secs 

Total REAL time to Placer completion: 4 secs 
Total CPU  time to Placer completion: 3 secs 
Running post-placement packing...
Writing output files...

Design Summary:
Number of errors:      0
Number of warnings:    0
Slice Logic Utilization:
  Number of Slice Registers:                     0 out of  11,440    0%
  Number of Slice LUTs:                          0 out of   5,720    0%

Slice Logic Distribution:
  Number of occupied Slices:                     0 out of   1,430    0%
  Number of MUXCYs used:                         0 out of   2,860    0%
  Number of LUT Flip Flop pairs used:            0

IO Utilization:
  Number of bonded IOBs:                         2 out of     102    1%
    Number of LOCed IOBs:                        2 out of       2  100%

Specific Feature Utilization:
  Number of RAMB16BWERs:                         0 out of      32    0%
  Number of RAMB8BWERs:                          0 out of      64    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                       0 out of      16    0%
  Number of DCM/DCM_CLKGENs:                     0 out of       4    0%
  Number of ILOGIC2/ISERDES2s:                   0 out of     200    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     200    0%
  Number of OLOGIC2/OSERDES2s:                   0 out of     200    0%
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHs:                               0 out of     128    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            0 out of      16    0%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       2    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            0 out of       2    0%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%

Average Fanout of Non-Clock Nets:                0.00

Peak Memory Usage:  650 MB
Total REAL time to MAP completion:  4 secs 
Total CPU time to MAP completion:   4 secs 

Mapping completed.
See MAP report file "rio.mrp" for details.
par -w rio.ncd parout.ncd rio.pcf
Release 14.7 - par P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.



Constraints file: rio.pcf.
Loading device for application Rf_Device from file '6slx9.nph' in environment /data/opt/Xilinx/14.7/ISE_DS/ISE/.
   "rio" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -3

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
   internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
   reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
   Note: For the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high".

Device speed data version:  "PRODUCTION 1.23 2013-10-13".



Device Utilization Summary:

Slice Logic Utilization:
  Number of Slice Registers:                     0 out of  11,440    0%
  Number of Slice LUTs:                          0 out of   5,720    0%

Slice Logic Distribution:
  Number of occupied Slices:                     0 out of   1,430    0%
  Number of MUXCYs used:                         0 out of   2,860    0%
  Number of LUT Flip Flop pairs used:            0

IO Utilization:
  Number of bonded IOBs:                         2 out of     102    1%
    Number of LOCed IOBs:                        2 out of       2  100%

Specific Feature Utilization:
  Number of RAMB16BWERs:                         0 out of      32    0%
  Number of RAMB8BWERs:                          0 out of      64    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                       0 out of      16    0%
  Number of DCM/DCM_CLKGENs:                     0 out of       4    0%
  Number of ILOGIC2/ISERDES2s:                   0 out of     200    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     200    0%
  Number of OLOGIC2/OSERDES2s:                   0 out of     200    0%
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHs:                               0 out of     128    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            0 out of      16    0%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       2    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            0 out of       2    0%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%


Overall effort level (-ol):   Standard 
Router effort level (-rl):    High 

Starting initial Timing Analysis.  REAL time: 2 secs 
Finished initial Timing Analysis.  REAL time: 2 secs 

WARNING:Par:288 - The signal sysclk_in_IBUF has no load.  PAR will not attempt to route this signal.
Starting Router


Phase  1  : 1 unrouted;      REAL time: 2 secs 

Phase  2  : 1 unrouted;      REAL time: 2 secs 

Phase  3  : 0 unrouted;      REAL time: 3 secs 

Phase  4  : 0 unrouted; (Par is working to improve performance)     REAL time: 3 secs 

Updating file: parout.ncd with current fully routed design.

Phase  5  : 0 unrouted; (Par is working to improve performance)     REAL time: 3 secs 

Phase  6  : 0 unrouted; (Par is working to improve performance)     REAL time: 3 secs 

Phase  7  : 0 unrouted; (Par is working to improve performance)     REAL time: 3 secs 

Phase  8  : 0 unrouted; (Par is working to improve performance)     REAL time: 3 secs 

Phase  9  : 0 unrouted; (Par is working to improve performance)     REAL time: 3 secs 

Phase 10  : 0 unrouted; (Par is working to improve performance)     REAL time: 3 secs 
Total REAL time to Router completion: 3 secs 
Total CPU time to Router completion: 3 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.
INFO:Par:459 - The Clock Report is not displayed in the non timing-driven mode.
Timing Score: 0 (Setup: 0, Hold: 0)



Generating Pad Report.

All signals are completely routed.

WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

Total REAL time to PAR completion: 3 secs 
Total CPU time to PAR completion: 3 secs 

Peak Memory Usage:  602 MB

Placer: Placement generated during map.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 3
Number of info messages: 2

Writing design to file parout.ncd



PAR done!
#bitgen -w -g StartUpClk:CClk -g CRC:Enable parout.ncd rio.bit rio.pcf
bitgen -w -g StartUpClk:jtagclk -g CRC:Enable parout.ncd rio.bit rio.pcf
Release 14.7 - Bitgen P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
Loading device for application Rf_Device from file '6slx9.nph' in environment
/data/opt/Xilinx/14.7/ISE_DS/ISE/.
   "rio" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -3
Opened constraints file rio.pcf.

Thu Jun 27 15:03:00 2024

Running DRC.
DRC detected 0 errors and 0 warnings.
Creating bit map...
Saving bit stream in "rio.bit".
Bitstream generation is complete.
cp -v hash_new.txt hash_compiled.txt
'hash_new.txt' -> 'hash_compiled.txt'