ColorCNC Colorlight 5A-75E/5A-75B as FPGA controller board

The option for flashing in the eeprom is -f, I'm using this command:
openFPGALoader --unprotect-flash -c ft232 -f Lcnc.bit

So if I remember correctly, J9-1 and J9-2 are step and direction of stepgen zero for your confiiguration.
Do you have a multimeter to check if the board is geenrating any voltage on these pins?
I would start with the simplest configuration possible:
Use HAL.hal in support files, use halshow to check the pins status and set them manually. Start first with the board enabling sequence, as expained in the readme, then adde all the pins and parameters of the stepgen 0 and if everything is right once you set the velocity command to a value other than zero you should see the position feedback in halshow change and see the pulses on the pins. If there are no pulses but the position is changing then maybe there is some problem in your pin mapping.

The voltage of J9-1 only fluctuates by 1-2V, and J9-2 will fluctuate by 3-6V. Because the power supply I use is 6.2V, it will only be generated when running the code. I tested it in jog mode, and J9- 1 and J9-2 are the Z axis, J9-3 and J9-5 are the Y axis, 67 is the X axis

It's ready to run. It's my wiring problem

I tested it. When running the code, I found that the value of the G54 coordinates will always be offset by 0.01, sometimes it will become larger and sometimes it will be smaller.

Lcnc driver from @muvideo has some position error that has to be compensated by PID regulator. Litexcnc driver and firmware has negligible static position error but some dynamic error, that depends on jitter.

Firstly great work on this project folks.
I had great fun playing with 7i43 and Pluto cards many years back while upgrading my Denford CNC machines.

In advance please note I am rather green when it comes to surface mounted tech.

I have a question regarding package size of the output it's.
In previous threads it mention soic, I ordered some SN74LVC245ADW around the same time I ordered the 5A-75B (v8) for input level shifting but on arrival the SN74LVC245ADW have far to large a footprint than the existing 74HC245T located on the board.

I have around a zillion billion browser tabs open to data sheets while trying to figure out exactly what package is required for a drop in replacement and I have just lost my mind along with the will to live.

If I could add a emoji it would be an exploding head!

可以把你的驱动和固件发下吗

setp pid.1.deadband 0.00001，The parameter has been modified and the position is correct

Hi, I have used SN74LVC245APWR, the package should be tssop-20

romanetz wrote:

I noticed such a strange behavior of board: it accidentally stops to respond to incoming packets. Even for icmp. Unplugging with following plugging of ethernet cable recovers normal operation.

I still have trouble to have a consistent timing of the board. Don't know which part of the toolchain is causing this trouble. I found that running the toolchain (Yosys, etc) leads to different timing constraints. To start debugging I'm going to reduce the clock speed a bit and modify the stepgen to have the bit-shift determined dynamically based on the clock-speed. For example:

• with 40 Mhz and target maximum step frequency of 400 kHz the applied shift should 6 bits (63), because 40 Mhz / 128 = 629 kHz.
• with 20 Mhz the applied shift should be 5 bits (32) to get to the same speed.

With this change the accuracy and maximum step rate is no longer related to the clock-speed of the device. Choosing the bit-shift too small reduces accuracy, too large will reduce speed. To align driver and firmware the chosen clock-speed will be communicated when the card is reset / booted. As an option I'm thinking to let users define their own maximum step-frequency for the steppers (for example, some people will use less potent drives, but can gain on accuracy in that case).

Request:
Does any have a decent CAD drawing of the 5A-75B and 5A-75E with accurate position of the HUB-75 headers. Still playing with the idea of creating a hat...