ColorCNC Colorlight 5A-75E/5A-75B as FPGA controller board

Can you share any machine config for litexcnc?

In the documentation I included now examples for the 5A-75B, with in total 6 configurations:

• different version of the board (V6.1, V7.0 and V8.0)

combination of GPIO, PWM, StepGen and Encoders or GPIO only.

For the configuration I've added both indexed versions and named versions. In the named version the name of the pin is the physical position, i.e. pin j1:1 is pin 1 on the first connector. Tomorrow I'll upload some more examples for the 5A-75E. 

When compiling one of the examples I noticed timing issues when using 6 stepgens. Perhaps the board has to be throttled down to 25 MHz to meet the timing requirements. Timing wise the board can be throttled back way further. However this requires some changes on the pre-scaler of the stepgen. This one is now fixed for 400 kHz max step rate @ 50 MHz clock. I think the pre-scaler should be more flexible and automatically adapt itself when lower clock-speeds are used.

Can you share us your machine config? I can't understand (without deep penetration into the sources, heh) how to deal with velocity-cmd1 and velocity-cmd of stepgens, the same approach with acceleration. And, regarding S-curve implementation (which is, in fact, changing acceleration with some slope, not instantly) , do I need to modify motion planner and/or include some additional components into the signal path in HAL?
Also I've noticed some hang up of the boards when Linuxcnc failed to load and the driver has been terminated. After reconnection of ethernet cable, normal operation is restored.
And another trouble, maybe, mostly related to my setup - I see very many alerts informing me that apply time has been overwhelmed. in HAL statistics maximum read time reaches 23 msec, although in a latency test the jitter is in range of dozens of microseconds (max. 20 microsecond).

At this moment I cannot reach my machine config, as I'm not able the coming days to go to the machine. For wiring up the stepgen I would like to refer to the manual , which gives on how to use the components pos2vel and stepgen together. This example should work out of the box. You can expand it to the number of stepgens required.

About the apply_time not met. You can ignore these messages for now. You will get teh warning one time on-screen, most likely due to a stretched cycle. I will update the source code whether the apply time is too slow or too fast. Maybe (not sure) it has to do with the reduced clock-speed of the FPGA.

Did you succeed to compile the JSON on your machine using the tools? How long did the build take? I'm building inside a Docker container and it takes ages....

 

Well, the firmware compilation on my PC takes 5-10 minutes. PlaceNRouting is the most time consuming process. With 6 encoders, 6 stepgens, 12DI 12DO 3PWM the firmware doesn't meet timing requirements. But, in generally, rather close to them (38,4 instead of 40 Mhz and 114,5 instead of 125 Mhz).

romanetz wrote:

Well, the firmware compilation on my PC takes 5-10 minutes. PlaceNRouting is the most time consuming process. With 6 encoders, 6 stepgens, 12DI 12DO 3PWM the firmware doesn't meet timing requirements. But, in generally, rather close to them (38,4 instead of 40 Mhz and 114,5 instead of 125 Mhz).
 

That sounds a whole different story from what my PC is doing now. Just to check, you have modified one of the Json files to make your own config and build it with Litex-CNC? Could you share that config so I can test my build system? 

Here is my JSON, used for firmware compilation.

This is getting very strange:
I think my building system is splunked, because:

• the timings have failed worse then in your case;
• the build time is again exploding in my face (think it is related with the first case).

@romanetz: what is your toolchain you're using (i.e. version/branch of LitexCNC, Litex, Yosys, OSS-CAD-Suite). Dis you install the toolchain using the commands from LitexCNC or did you install it yourself? 

I'm not sure if I use the latest version.
Yosys 0.16+61 (git sha1 c785cb7fe, clang 10.0.0-4ubuntu1 -fPIC -Os)
nextpnr-ecp5 -- Next Generation Place and Route (Version nextpnr-0.3-14-g20cfafa1)
Project Trellis ecppack Version 1.0-496-g7454564

Info: Max frequency for clock                 '$glbnet$crg_clkout0': 43.53 MHz (PASS at 40.00 MHz)
Warning: Max frequency for clock '$glbnet$eth_clocks_rx$TRELLIS_IO_IN': 116.63 MHz (FAIL at 125.00 MHz)

 

Well. I've found some description of the network protocol that is implemented in original firmware.
hkubota.wordpress.com/2022/01/31/winter-...ght-5a-75b-protocol/
The goal of further investigation is to provide some kind of utility to convert colorlight card into litexcnc (so, in-system programming) without any soldering.