I noticed such a strange behavior of board: it accidentally stops to respond to incoming packets. Even for icmp. Unplugging with following plugging of ethernet cable recovers normal operation.
I still have trouble to have a consistent timing of the board. Don't know which part of the toolchain is causing this trouble. I found that running the toolchain (Yosys, etc) leads to different timing constraints. To start debugging I'm going to reduce the clock speed a bit and modify the stepgen to have the bit-shift determined dynamically based on the clock-speed. For example:
- with 40 Mhz and target maximum step frequency of 400 kHz the applied shift should 6 bits (63), because 40 Mhz / 128 = 629 kHz.
- with 20 Mhz the applied shift should be 5 bits (32) to get to the same speed.
With this change the accuracy and maximum step rate is no longer related to the clock-speed of the device. Choosing the bit-shift too small reduces accuracy, too large will reduce speed. To align driver and firmware the chosen clock-speed will be communicated when the card is reset / booted. As an option I'm thinking to let users define their own maximum step-frequency for the steppers (for example, some people will use less potent drives, but can gain on accuracy in that case).
Request:
Does any have a decent CAD drawing of the 5A-75B and 5A-75E with accurate position of the HUB-75 headers. Still playing with the idea of creating a hat...
