LinuxCNC-RIO - RealtimeIO for LinuxCNC based on FPGA (ICE40 / ECP5)

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05 Aug 2024 11:49 #306990 by meister
@all

how do you implement differential signals?
i wanted to try it now with the AM26LS32, there are also some from MAX but they are extremely expensive

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05 Aug 2024 14:28 #307001 by PCW
We use 26LS32's a lot for a couple of reasons:

1. Their inputs are protected from up to +-25V
(the more expensive CMOS parts are typically protected to only +-14V or so)

2. Because they are TTL parts the outputs don't swing to 5V and if you add a 1K
pulldown, the outputs are OK for interfacing with most 3.3V chips.

3. They are much cheaper than  the CMOS equivalents.

The main disadvantage is higher power consumption
The following user(s) said Thank You: tommylight, meister, Mecanix

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05 Aug 2024 16:09 #307008 by meister
thank you PCW !

the Linear Scale works with quadencoder(z) plugin :)

but the part from my link is really cheap,
ok for playing around, but to use it properly, hmm, no

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05 Aug 2024 16:36 #307010 by Mecanix

new toy :)
works like a rotary-encoder, i think it should work in RIO

Haha that's so cool. Their output are indeed identical to those 90deg ABZ rotary encoder. Plugs right in your quadencoderz plugin and so no extra work required!

In the other RIO gossips; a brand new journey is about to begin!! However and before I begin routing this I wanted to poke your expertise and ask what would define a half-perfect RIO Motion Control Board. Is there anything fancy that we need on that other than the usual SPINDLE + MPG + XYZAB + Ins & Outs? 

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05 Aug 2024 21:35 #307034 by meister
Sorry, was busy :)



@Mecanix
nice board !, but i answer you tomorrow, need sleep now
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06 Aug 2024 05:39 - 06 Aug 2024 06:29 #307058 by meister
>In the other RIO gossips; a brand new journey is about to begin!! However and before I
>begin routing this I wanted to poke your expertise and ask what would define a half-
>perfect RIO Motion Control Board. Is there anything fancy that we need on that other
>than the usual SPINDLE + MPG + XYZAB + Ins & Outs?

it always depends on the application,
as a universal board, I would say:

4 step/dir
4 inputs (selectable 24V/5V - Proximity Limit Switch)
1 encoder (for lathe / with differantal inputs)
>=3 inputs (for estop/misc)
>=3 outputs (cooling/spindle)
1 MODUS (vfd-spindle)
1 WS2812b (status display / only one pin needed)
1 PMOD header


I really like these connectors: www.reichelt.de/stiftleiste-2-pol-rm-3-5...rank&OFFSET=16&nbc=1
but it's a matter of taste :)

i think USB/Seriel is not necessary

the fpga on the tangnano20k has the same housing, if the pinout matches you could also use it !?!?!
not the same :(

EDIT: and it should work with cheap programmer like the USB-Blaster
 
Last edit: 06 Aug 2024 06:29 by meister.
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06 Aug 2024 07:32 - 06 Aug 2024 07:36 #307059 by meister
i have noticed that you can also generate verilog with litex without soft-core. and that liteeth also supports UDP in hardware. I think it should be possible to build a UDP interface that runs on the Colorlite boards (and others) and can be integrated into RIO.

There are many supported FPGA's and PHY's: github.com/enjoy-digital/liteeth
Last edit: 06 Aug 2024 07:36 by meister.

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06 Aug 2024 07:59 #307060 by kzali

i have noticed that you can also generate verilog with litex without soft-core. and that liteeth also supports UDP in hardware. I think it should be possible to build a UDP interface that runs on the Colorlite boards (and others) and can be integrated into RIO.

There are many supported FPGA's and PHY's: github.com/enjoy-digital/liteeth

Would the Tang Primer 20k be a good candidate

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06 Aug 2024 08:04 #307061 by meister
unfortunately i don't know much about litex and i don't know if it is supported.

but for the tangprimer20k on the dock ext-board there is already a plugin in RIO:

github.com/multigcs/riocore/tree/dev/riocore/plugins/rmii

but not much tested

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06 Aug 2024 08:13 #307062 by meister
i tried to generate a simple udp core and the interface looks very simple:
module liteeth_core (
    input  wire          rgmii_clocks_rx,
    output wire          rgmii_clocks_tx,
    input  wire          rgmii_int_n,
    output wire          rgmii_mdc,
    input  wire          rgmii_mdio,
    output wire          rgmii_rst_n,
    input  wire          rgmii_rx_ctl,
    input  wire    [3:0] rgmii_rx_data,
    output wire          rgmii_tx_ctl,
    output wire    [3:0] rgmii_tx_data,

    input  wire          sys_clock,
    input  wire          sys_reset,

    input  wire   [31:0] udp0_sink_data,
    input  wire          udp0_sink_last,
    output wire          udp0_sink_ready,
    input  wire          udp0_sink_valid,

    output wire   [31:0] udp0_source_data,
    output wire          udp0_source_error,
    output wire          udp0_source_last,
    input  wire          udp0_source_ready,
    output wire          udp0_source_valid
);
rgmi_* and sys_* are the FPGA-Pins
udp0_sink and udp0_source the data interface for RX and TX

it looks feasible to connect the whole thing to rio :)
 

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